• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.11-21
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• 1999

This paper has been proposed a structure composed of FIRs and IIR filters as digital interpolation filter to integrate the off-chip analog low-pass filter of audio DAC. The passband ripple (>$0.41{\times}fs$), passband attenuation(>at$0.41{\times}fs$) and stopband attenuation(<$0.59{\times}fs$) of the ${\Delta}{\Sigma}$ modulator output using the proposed digital interpolation filter had ${\pm}0.001[dB]$, -0.0025[dB] and -75[dB], respectively. Also the inband group delay was 30.07/fs[s] and the error of group delay was 0.1672%. Also, the attenuation of stopband has been increased -20[dB] approximately at 65[kHz], out-of-band. Therefore the RC products of analog low-pass filter on chip have been decreased compared with the conventional digital interpolation filter structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.31-36
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• 2004

In this paper, we proposed the new structure of the Rake Finger using Walsh Switch, the shared accumulator, and the pipeline-FWHT algorithm for reducing the signal processing complexity resulting from the increase of the number of data correlator. The function simulation of the proposed architecture is performed by Synopsys tool and the timing simulation is performed by Compass tool. The number of computational operation in the proposed data correlators is 160 additions and the conventional ones is 512 additions when the number of walsh code N=4. As a result, it is reduced about 3.2 times other than the number of computational operation of the conventional ones. Also, the result shows that the data processing time of the proposed Rake Finger architecture is 90,496[ns] and the conventional ones is 110,696[ns]. It is $18.3\%$ faster than the data processing time of the conventional Rake Finger architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.371-381
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• 2005

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.148-156
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• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.141-148
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• 2004

Recently, the demand of broadband communications such as high-speed internet, HDTV, 3D-HDTV and ATM backbone network has been increased drastically. For transmitting the broad-bandwidth data using wireless network, it is needed to use ka-band frequency. However, the use of this ka-band frequency is seriously affected to the received data performance by rain fading and atmospheric propagation loss at the Ka-band satellite communication link. So, we need adaptive MODEM to endure the degraded performance by channel environment. In this paper, we will present the structure and design of the 155Mbps adaptive Modem adaptively compensated against channel environment. In order to compensate the rain attenuation over the ka-band wireless channel link, the adaptive coding schemes with variable coding rates and the multiple modulation schemes such as trellis coded 8-PSK, QPSK, and BPSK are adopted. And the blind demodulation scheme is proposed to demodulate without Information of modulation mode at the multi-mode demodulator, and the fast phase ambiguity resolving scheme is proposed. The design and simulation results of adaptive Modem by SPW model are provided. This 155Mbps adaptive MODEM was designed and implemented by single ASIC chip with the $0.25\mu{m}$ CMOS standard cell technology and 950 thousand gates.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.38-48
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• 2014

In this paper, a design of Signal Processing Analog Front-End IC for Automotive Piezo-Resistive Type Pressure Sensor is presented. In modern society, as the car turns to go from mechanical to electronic technology, the accuracy and reliability of electronic parts required importantly. In order to improve these points, Programmable Gain Amplifier (PGA) amplifies the received signal in accordance with gain for increasing the accuracy after PRT Sensor is operated to change physical pressure signals to electrical signals. The signal amplified from PGA is processed by Digital blocks like ADC, CMC and DAC. After going through this process, it is possible to determine the electrical signal to physical pressure signal. As processing analog signal to digital signal, reliability and accuracy in Analog Front-End IC is increased. The current consumption of IC is 5.32mA. The die area of the fabricated IC is $1.94mm{\times}1.94mm$.

• The Bulletin of The Korean Astronomical Society
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• v.39 no.1
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• pp.52.2-52.2
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• 2014

The Immersion Grating Infrared Spectrometer (IGRINS) is an unprecedentedly minimized infrared cross-dispersed echelle spectrograph with a high-resolution and high-sensitivity optical performance. A silicon immersion grating features the instrument for the first time in this field. IGRINS will cover the entire portion of the wavelength range between 1.45 and $2.45{\mu}m$ accessible from the ground in a single exposure with spectral resolution of 40,000. Individual volume phase holographic (VPH) gratings serve as cross-dispersing elements for separate spectrograph arms covering the H and K bands. On the 2.7m Harlan J. Smith telescope at the McDonald Observatory, the slit size is $1^{\prime\prime}{\times}15^{\prime\prime}$. IGRINS has a $0.27^{\prime\prime}$ pixel-1 plate scale on a $2048{\times}2048$ pixel Teledyne Scientific & Imaging HAWAII-2RG detector with SIDECAR ASIC cryogenic controller. The instrument includes four subsystems; a calibration unit, an input relay optics module, a slit-viewing camera, and nearly identical H and K spectrograph modules. The use of a silicon immersion grating and a compact white pupil design allows the spectrograph collimated beam size to be 25mm, which permits the entire cryogenic system to be contained in a moderately sized rectangular vacuum chamber. The fabrication and assembly of the optical and mechanical hardware components were completed in 2013. In this presentation, we describe the major design characteristics of the instrument and the early performance estimated from the first light commissioning at the McDonald Observatory.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.444-447
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• 2011

In this paper, parallel IT(inverse transform) architecture and IQ(inverse quantization) architecture with common operation unit for the H.264/AVC decoder are proposed. By using common operation unit, the area cost and computational complexity of IQ are reduced. In order to take four execution cycles to perform IT, the proposed IT architecture has parallel architecture with one horizontal DCT unit and four vertical DCT units. Furthermore, the execution cycles of the proposed architecture is reduced to five cycles by applying two state pipeline architecture. The proposed architecture is implemented to a single chip by using Magnachip 0.18um CMOS technology. The gate count of the proposed architecture is 14.3k at clock frequency of 13MHz and the area of proposed IQ is reduced 39.6% compared with the previous one. The experimental result shows that execution cycle the proposed architecture is about 49.09% higher than that of the previous one.

• The Bulletin of The Korean Astronomical Society
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• v.39 no.2
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• pp.90-90
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• 2014

The Immersion Grating Infrared Spectrometer (IGRINS) is the first astronomical spectrograph that uses a silicon immersion grating as its dispersive element. IGRINS fully covers the H and K band atmospheric transmission windows in a single exposure. It is a compact high-resolution cross-dispersion spectrometer whose resolving power R is 40,000. An individual volume phase holographic grating serves as a secondary dispersing element for each of the H and K spectrograph arms. On the 2.7m Harlan J. Smith telescope at the McDonald Observatory, the slit size is $1^{{\prime}{\prime}}{\times}15^{{\prime}{\prime}}$. IGRINS has a plate scale of 0.27" pixel-1 on a $2048{\times}2048$ pixel Teledyne Scientific & Imaging HAWAII-2RG detector with a SIDECAR ASIC cryogenic controller. The instrument includes four subsystems; a calibration unit, an input relay optics module, a slit-viewing camera, and nearly identical H and K spectrograph modules. The use of a silicon immersion grating and a compact white pupil design allows the spectrograph collimated beam size to be 25mm, which permits the entire cryogenic system to be contained in a moderately sized ($0.96m{\times}0.6m{\times}0.38m$) rectangular Dewar. The fabrication and assembly of the optical and mechanical components were completed in 2013. From January to July of this year, we completed the system optical alignment and carried out commissioning observations on three runs to improve the efficiency of the instrument software and hardware. We describe the major design characteristics of the instrument including the system requirements and the technical strategy to meet them. We also present the instrumental performance test results derived from the commissioning runs at the McDonald Observatory.