• The Journal of the Acoustical Society of Korea
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• v.12 no.1
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• pp.27-36
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• 1993

FM방식의 악기음원합성은 해당 악기의 음색과 음정에 맞는 FM의 기본 주파수와 변조 계수를 정하여 신호 파형을 생성하는 것으로, 다른 가, 감산방식 또는 PCM방식 등에 비해 비교적 간단한 구조로 다양한 악기음원합성이 가능하다. 따라서 현재 사용되고 있는 개인용 컴퓨터에 부착되는 사운드합성 카드에는 FM방식 음원합성기술이 적용되고 있다. 본 논문에서는 FM방식 음원합성기술을 이용하여 실시간 악기음원합성이 가능한 논리회로를 설계하는데 관한 연구를 기술한다. 본 연구에서는 소프트웨어 프로그래밍에 의해 FM방식 음원합성기의 구조를 설계하고 주요 블록의 최적 변수 값을 실험하였다. 논리회로 설계 및 회로검증은 향후 주문형반도체(ASIC:Application Specific Integrated Circuit)제작을 위해 기존의 표준셀 라이브러리와 주문형반도체 전용 설계시스템을 사용하였다. 회로검증 결과는 간이 평가보드를 제작하고 PC와 접속시켜 생성된 악기음을 직접듣는 주관적 평가방법으로 최종 확인하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10d
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• pp.502-505
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• 2006

본 논문은 고해상도의 영상을 처리하는 이동기기 등에 사용되는 SoC(System On a Chip)에 구현이 용이한 효과적인 화질 향상 (잡음감소와 윤곽강조) 을 위한 방법과 구조에 대한 것이다. 최근 이동기기의 발전과 진화에 따라 여러 형태의 이동기기가 개발되고 있는데 그 중 최근 인기를 끌고 있는 포터블 미디어 플레이어 (PMP)나 HD(Hight Definition)급 camcorder 등이 고해상도의 영상을 처리하는 이동기기로 분류될 수 있다. 이러한 이동기기에서 고해상도 영상에 대한 화질 향상을 기존의 복잡한 방법을 사용해 처리한다면 메모리 대역폭이나 하드웨어 크기 등의 증가로 이동기기에서 구현하는데 어려움이 따른다. 이에 본 논문에서는 이러한 이동기기에서의 고해상도의 화질 향상을 입력영상의 종류에 따라 선택적으로 메모리 대역폭 사용 없이 하드웨어 크기를 최소화하여 FPGA (field programmable gate array)나 ASIC (application specific integrated circuit)으로 구현이 용이하도록 하는 방법과 구조에 대해 설명하고 실제 영상을 가지고 실험한 결과로 주관적 화질 향상 효과를 가져 온 것을 확인할 수 있었다.

• Journal of the Korean Society of Marine Environment & Safety
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• v.20 no.3
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• pp.318-322
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• 2014

A kind of field bus called Actuator and Sensor interface bus(AS-i) was designed in this paper. The configuration of AS-i network system used Application Specific Integrated Circuit(ASIC) SAP5S chip and PLC S7-200 station, which included CPU 224 and AS-i master module CP 243-2. We also created an example program for PLC S7-200 to control AS-i network. The fire and smoke detection system was made with AS-i network system that was designed. This system had got more advantages than other system such as number of stations, easy installation, wide working area, etc. And designed system can be used as a partner network for higher level field bus networks.

• Journal of Korea Multimedia Society
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• v.23 no.2
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• pp.317-327
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• 2020

R&D(Research and Development) efficiency analysis is a very important issue in academia and industry. Although many studies have been conducted to analyze R&D(Research and Development) efficiency since the past, studies that analyzed R&D(Research and Development) efficiency considering both patentability and patent quality efficiency according to the financial performance of a company do not seem to have been actively conducted. In this study, measuring the patent application and patent quality efficiency according to financial performance, patent quality efficiency according to patent application were applied to corporate groups related to artificial intelligence hardware technology defined as GPU(Graphics Processing Unit), FPGA(Field Programmable Gate Array), ASIC(Application Specific Integrated Circuit) and Neuromorphic. We analyze the efficiency empirically and use Data Envelopment Analysis as a measure of efficiency. This study examines which companies group has high R&D(Research and Development) efficiency about artificial intelligence hardware technology.

• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• Journal of Electrical Engineering and Technology
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• v.1 no.1
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• pp.63-72
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• 2006

The purpose of this raper is to address the negative impedance instability in DC/DC converters. We present the negative impedance instability of PWM DC/DC converters loaded by constant power loads (CPLs). An approach to design digital controllers for DC/DC converters Is presented. The proposed method, called Power Alignment control technique, is applied to DC/DC step-down choppers operating in continuous conduction or discontinuous conduction modes with CPLs. This approach uses two predefined state variables instead of conventional pulse width modulation (PWM) to regulate the output voltage. A comparator compares actual output voltage with the reference and then switches between the appropriate states. It needs few logic gates and comparators to be implemented thus, making it extremely simple and easy to develop using a low-cost application specific integrated circuit (ASIC) for converters with CPLs. Furthermore, stability of the proposed controllers using the small signal analysis as well as the second theorem of Lyapunov is verified. Finally, simulation and analytical results are presented to describe and verify the proposed technique.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Journal of Sensor Science and Technology
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• v.26 no.3
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• pp.179-185
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• 2017

This article describes the characteristics of nondispersive infrared carbon dioxide gas sensor according to the temperatures and humidifies. In this researches, a thermopile sensor that included application-specific integrated circuit (ASIC) was used and the White-cell structure was implemented as an optical waveguide. The developed sensor modules were installed in gas chamber and then the temperature of gas chamber has been increased from 283 K to 313 K with 10K temperature step. In order to analyze the effects of humidity levels, the relative humidity levels were changed from 30 to 80%R.H. with small humidifier. Then, the characteristics of sensor modules were acquired with the increment of carbon dioxide concentrations from 0 to 2,000 ppm. When the initial voltages of sensors were compared before and after humidifying the chamber at constant temperature, the decrements of the output voltages of sensors are like these: 9mV (reference infrared sensor), 41 mV (carbon dioxide sensor), 2 mV (temperature sensor). With the increment of ambient temperature, the averaged output voltage of carbon dioxide sensor was increased 19 mV, however, when the humidity level was increased, it was decreased 14mV. Based upon the experimental results, the humidity effect could be alleviated by the increment of temperature, so the effects of humidity and temperature could be only compensated by the ambient temperature itself. The estimated carbon dioxide concentrations showed 10% large errors below 200 ppm, however, the errors of the estimations of carbon dioxide concentrations were less than ${\pm}5%$ from 400 to 2,000 ppm.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.228-238
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• 2002

This paper presents a digital controller of the electronic ballast using high frequency modulation method for the metal halide lamp. The proposed controller includes the control algorithm for soft starting, no load protection, over current protection and power control. The proposed digital controller, moreover, has the high frequency modulation scheme and the tracking algorithm to avoid acoustic resonance phenomena. For the math production with the low cost using the ASICs (Application Specific Integrated Circuit), the proposed digital controller has been designed with the FPGAs(Field Programmable Gate array) only, without any microprocessor. In this paper, the detail digital control algorithms are described and the experimental results of prototype 150w metal halide electronic ballast are presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.