• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.839-842
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• 1998

The wide spread of multimedia system demands a large viewin gdesply device which can inform a message to many peoples in open area. This paper is about the design, simulating and testing of a large viewing LED pannel control ASIC(application specific integrated circuit). This LED pannel control ASIC runs on 16 bit microprocessor MC68EC000 and has following functions:16 line interlaced LED pannel controller, memory controller, 16 channel priority inerrupt controller, 2 channel direct memory access controller, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16byte FIFO, IBM PC/AT compatible keyboard interface, battery backuped real time clock, ISA bus controller, battery backuped 256 byte SRAM and watech dog timer. The 0.6micron CMOS sea of gate is used to design the ASIC in amount of about 39,000 gates.

• Annual Conference of KIPS
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• 2009.11a
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• pp.19-20
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• 2009

H.264 부호기의 on-chip 상의 구현방법으로는 성능에 중점을 둔 ASIC (application specific integrated circuit) 기반의 접근 방식과 ASIC 보다 성능은 떨어지나 일반성과 유연성에 중점을 둔 ASIP (application specific instruction set architecture) 기반의 설계 방식이 연구되어 왔다. 우리는 영상 압축 응용 범위 내에서는 일반성 및 유연성을 잃지 않으면서도 기존에 문제시 되던 ASIP의 성능은 대폭 개선할 수 있는 ISA와 micro architecture를 제안하고 구현한 바 있다. 본 논문의 핵심적인 기여는 이 ASIP의 추가적인 성능 개선이다.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.12
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• pp.67-75
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• 1999

In this paper, we present an ASIC(Application Specific Integrated Circuit) design of wavelet transform filter Wavelet transform is used in lots of application fields which include image compression, because it has an excellent energy compaction. The operation characteristic and performance of wavelet transform filter are analyzed by using verilog-HDL(Hardware Description Language). In this paper, the designed wavelet transform filter uses line memory to improve data processing rate. Generally, when it reads and writes data of DRAM by using Fast Page Mode, input and output processing is very fast in horizontal direction but substantially slow in vertical direction. The use of line memory solves this low speed processing problem. As a result, though the size of the chip is getting larger, processing time for an image frame becomes 4.66ms. Generally, since the limit of 1 frame processing time on the data of TV video is 33ms, so it is appropriate for TV video.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.7
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• pp.140-145
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• 1989

In this paper, we present an effective circuit placement method called SOAP (self-organization assisted placement) for rectilinear or arbitrarily-shaped region arised form the layout of ASIC (application specific integrated circuit). Self-organization is a learning algorithm for neural networks proposed by [1] which adjusts weights of synapses connected to neurons such that topologically close neurons are sensitive to inputs that are physically similar. In SOAP, we obtain a good circuit placement result in arbitrarily-shaped region by replacing the block of circuit and the position (x, y coordinates) of the block with the neuron and the weight pair of synapses connected to the neuron, respectively. This method can also be extended to the circuit placement over the nonplanar surface.

• Proceedings of the KOSOMBE Conference
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• v.1998 no.11
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• pp.299-300
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• 1998

Recently the development of medical modality like as MRI, 3D US, DR etc is very active. Therefore it is more required not only the enhancement of quality in medical service but the improvement of medical system based on quantization, minimization, and optimization of high speed. Especially, as the changing into the digital modality system, it gets to start using ASIC(Application Specific Integrated Circuit) to realize one board system. It requires the implementation of hardware debugging and effective speedy algorithm with more speed and accuracy in order to support and replace existing device. If objected image could be linked to high speed process board with special interface and pre-processed using FPGA, it can be used in real time image processing and protocol of HIS(Hospital Information System). This study can support the basic circuit design of medical image board which is able to realize image processing basically using digitalized medical image, and to interface between existing device and image board containing image processing algorithm.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2680-2700
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• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11C
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• pp.1102-1110
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• 2007

In this paper, we design the FPGA (Field-Programmable Gate Array) of the CAMB (Constant-Amplitude Multi-code Biorthogonal) modulation, and implement the SoC (System on Chip). The ASIC (Application Specific Integrated Circuit) chip is be implemented through targeting and board test. This 12Mbps modem SoC includes the ARM (Advanced RISC Machine)7TDMI, 64Kbyte SRAM(Static Random Access Memory) and ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter) for flexible applications. Additionally, the modem SoC can support the variable communication interfaces such as the 16-bits PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus) 1.1, and 16C550 Compatible UART (Universal Asynchronous Receiver/Transmitter).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.321-327
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• 2006

This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

• Journal of the Korea Computer Graphics Society
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• v.6 no.3
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• pp.1-7
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• 2000

The number of pixels being processed in a raster graphics system often exceeds 1 million per frame. Replacing fractional arithmetic by integer arithmetic on rendering graphics primitives will therefore significantly improve the rendering performance. A scaling method that replaces fractional arithmetic by integer arithmetic on rendering graphics primitives is introduced. This method is applied to the filtered edge drawing and Gouraud shading. This method will also be applicable to some of other incremental algorithms for rendering graphics primitives. Because the scaling method requires only simple modifications upon the known algorithms that already have been implemented in ASIC (Application Specific Integrated Circuit), our algorithms can easily be implemented in ASIC. Our method will be useful especially for the low-price systems (e.g., home game machines, personal computers, etc.).

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.274-277
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• 1999

The paper describes a implementation of space vector pulse-width modulation (SVPWM) voltage source inverter using Field Programmable Gate Array(FPGA) for a induction motor control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QL16X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed FPGA for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance voltage source inverter drives. Simulation and Implementation results are shown to verify the usefulness of FPGA as a Application Specific Integrated Circuit(ASIC) in power electronics applications