• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.880-882
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• 2005

소프트웨어 개발에 있어 가상 프로토타입의 활용은 하드웨어와의 병렬적인 개발 진행, 하드웨어 변경에 따른 신속한 대처, 확장된 디버깅과 벤치마킹 정보 등을 통해 개발 효율을 증대시킨다. 본 논문은 ARM을 기반하는 시스템의 소프트웨어 개발을 위한 가상 프로토타입 구현에 대해 다룬다. ARM사의 ADS1.2에서 제공하는 ARMulator의 Instruction Set Simulator를 기반하여 소프트웨어 개발자 관점의 추상화 수준으로 System-on-chip인 삼성 S3C2400의 축소된 형태를 가정하여 가상 프로토타입을 설계 및 구현하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.592-594
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• 2004

프로토타입핑은 제품 개발을 위한 필요한 과정이지만 실제로 제품의 모형을 만든 후에 외형 및 기능을 검사하기 때문에 제품 개발 시간과 비용이 많이 들게 된다 컴퓨터 기술을 이용한 가상 프로토타이핑 시스템은 이러한 단점을 보안하기 때문에 않은 연구가 되고 있다 본 논문에서는 내장형 시스템 개발용 가상 프로토타입 플렛폼 제작을 위해 PDA와 휴대형 단말장치에서 가장 많이 사용되는 ARM코어를 기반으로 하는 ARMulator상에 하드웨어 IP를 구현하고 실시간 운영교제인 UC/OS-11를 이식하여 내장형 소프트웨어 개발용 가상 프로토타이핑의 환경을 구축하였다. 세 개의 타스크로 구성된 검사 프로그램를 운영하여 구축된 시스템의 동작을 확인하였다. 구축된 시스템은 내장형 시스템의 소프트웨어 개발을 위한 가상 환경을 제공한다.

• The Journal of the Korea Contents Association
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• v.10 no.1
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• pp.59-67
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• 2010

Laboratory works for embedded system courses are usually performed with hardware based experimental kits that equipped with an embedded board and software development tools. Hardware-based kits have demerits such as high initial setup cost, burdensome maintenance, inadaptability to industry evolution, and restricted educational outcomes. This paper proposes using virtual experimental environments to overcome the demerits of hardware-based kits and describes the design and implementation of a simulation-based virtual experimental kit. With ARM's ARMulator, we developed the kit by adding hardware IPs and user interface modules for peripherals. The developed kit is verified with an experimental program that uses all the augmented software modules. We also ported MicroC/OS-II on the virtual experimental kit for real-time OS experiments.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.6
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• pp.82-92
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• 2001

This paper describes implementation of an embedded 32-Bit RISC core for portable communication/information equipment, such as cellular phones, PDA(Personal Digital Assistants), notebook, etc. The RISC core implements the ARM$\circled$V 4 instruction set, operates with typical 5-stage pipeline. It supports Thumb code to improve the code density, and uses the dynamic power management method of pipeline registers. It was modeled and simulated in RTL level using VHDL, and verified with ARMulator of ADS (Arm Developer Suite) and had average CPI of 1.44. The core is synthesized automatically using the cell library based on $0.6{\mu}m$ CMOS 1-poly 3-metal CMOS technology. It consists of about 41,000 gates and the clock frequency is expected to be above 45 MHz.

• 전자공학회논문지 IE
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• v.47 no.1
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• pp.48-55
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• 2010

The goal of this paper is to determine optimal hardware platform for specific applications. In order to develop an understanding of how select the optimal platform, we focus upon the real-time embedded vehicle system for processing forward image and sound. In this paper we propose to measure parameters such as instructions, execution cycle, required memory size for program and data by using ARMulator. We have measured three types of processor cores: ARM7, ARM9 and ARM10. The results of the study indicated that the proposed methods could measure the minimal requirements of hardware platform for specific applications. By defining lower limit of hardware specifications in embedded systems, we can minimize expenses with suitable system performance without implementing the system.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.325-328
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• 2002

In this paper, we present a SystemC model of a 32-Bit RISC core wi)ich is based on the ARMTTDMI architecture. The RISC core model was first modeled in C for architecture verification and then refined down to a level that allows concurrent behavior lot hardware timing using the SystcmC class library. It was driven in timed functional level that uses handshake protocol. It was compiled using standard C++ compiler. The functional simulation result was verified by comparing the contents of memory, the result of execution with the result from the ARMulator of ADS(Arm Developer Suite).

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.6
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• pp.30-35
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• 2007

H.264/AVC provides better quality than other algorithms by using a deblocking filter to remove blocking distortion on block boundary of the decoded picture. However, this filtering process includes lots of memory accesses, which cause delay of overall decoding time. In this paper, we propose a data-reuse algorithm to speed up the process for the deblocking filter. To reuse the data, a new filtering order is suggested. By using this order, we reduce the memory access and accelerate the deblocking filter. The modeling of proposed algorithm is compiled under ARM ADS1.2 and simulated with Armulator. The results of the experiment compared with H.264/AVC standard are achieved on average 58.45% and 57.93% performance improvements at execution cycles and memory access cycles, respectively.

• Journal of information and communication convergence engineering
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• v.8 no.6
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• pp.716-720
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• 2010

This paper proposes an effective fingerprint identification system with hardware block for thinning stage processing of a verification algorithm based on minutiae with 39% occupation of 32-bit RISC microprocessor cycle. Each step of a fingerprint algorithm is analyzed based on FPGA and ARMulator. This paper designs an effective hardware scheme for thinning stage processing using the Verilog-HDL in $160{\times}192$ pixel array. The ZS algorithm is applied for a thinning stage. The logic is also synthesized in $0.35{\mu}m$ 4-metal CMOS process. The layout is performed based on an auto placement-routing and post-simulation is performed in logic level. The result is compared with a conventional one.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.2
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• pp.26-32
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• 2008

Video compression schemes have been developed and used for many years. Currently, H.264/AVC is the most efficient video coding standard. The H.264/AVC baseline profile adopts CAVLC(Context-Adaptive Variable Length Coding) method as an entropy coding method. CAVLC gives better performance in compression ratios than conventional VLC(Variable Length Coding). However, because CAVLC decoder uses a lot of VLC tables, the CAVLC decoder requires a lot of area in terms of hardware. Conversely, since it must look up the VLC tables, it gives a worse performance in terms of software. In this paper, we propose a new hierarchical grouping method for the VLC tables. We can obtain an index of codes in the reconstructed VLC tables by simple arithmetic operations. In this method, the VLC tables are accessed just once in decoding a symbol. We modeled the proposed algorithm in C language, compiled under ARM ADS1.2 and simulated it with Armulator. Experimental results show that the proposed algorithm reduces execution time by about 80% and 15% compared with the H.264/AVC reference program JM(Joint Model) 10.2 and the arithmetic operation algorithm which is recently proposed, respectively.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.15-25
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• 2005

Embedded systems have a set of tasks to execute. These tasks can be implemented either on application specific hardware or as software running on a specific processor. The design of an embedded system involves the selection of hardware software resources, Partition of tasks into hardware and software, and performance evaluation. An accurate estimation of execution time for extreme cases (best and worst case) is important for hardware/software codesign. A tighter estimation of the execution time bound nay allow the use of a slower processor to execute the code and may help lower the system cost. In this paper, we consider an ARM-based embedded system and developed a tool to estimate the tight boundary of execution time of a task with loop bounds and any additional program path information. The tool we developed is based on an exiting timing analysis tool named 'Cinderella' which currently supports i960 and m68k architectures. We add a module to handle ARM ELF object file, which extracts control flow and debugging information, and a module to handle ARM instruction set so that the new tool can support ARM processor. We validate the tool by comparing the estimated bound of execution time with the run-time execution time measured by ARMulator for a selected bechmark programs.