• Nuclear Engineering and Technology
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• v.39 no.4
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• pp.287-298
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• 2007

As part of the $AP1000^{TM}$ pressurized water reactor design certification program, a series of integral systems tests of the nuclear steam supply system was performed at the APEX-1000 test facility at Oregon State University. These tests provided data necessary to validate Westinghouse safety analysis computer codes for AP1000 applications. In addition, the tests provided the opportunity to investigate the thermal-hydraulic phenomena expected to be important in AP1000 small-break loss of coolant accidents (SBLOCAs). The APEX-1000 facility is a 1/4-scale pressure and 1/4-scale height simulation of the AP1000 nuclear steam supply system and passive safety features. A series of eleven tests was performed in the APEX-1000 facility as part of a U.S. Department of Energy contract. In all, four SBLOCA tests representing a spectrum of break sizes and locations were simulated along with tests to study specific phenomena of interest. The focus of this paper is the SBLOCA tests. The key thermal-hydraulic phenomena simulated in the APEX-1000 tests, and the performance and interactions of the passive safety-related systems that can be investigated through the APEX-1000 facility, are emphasized. The APEX-1000 tests demonstrate that the AP1000 passive safety-related systems successfully combine to provide a continuous removal of core decay heat and the reactor core remains covered with considerable margin for all small-break LOCA events.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.91-100
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• 2004

In this paper, we propose the method that analyzes the depth of object using 2 images in the disparity algorithm. It also presents the design and implementation of the proposed method for a real time processing. The proposed system uses the vertical strip structure for calculating similar pixel numbers for the processing and converts the depth of object into gray scale images in order to be displayed on various display devices. The hardware using the proposed method is operating with 30 frames/sec and verified by using the Altera APEX 20K1000EBC652-3. The proposed method is also Implemented into It by using the Hynix 0.35${\mu}{\textrm}{m}$ CB35 ASIC library and 256PQFP package.

• Tribology and Lubricants
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• v.35 no.5
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• pp.286-293
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• 2019

In friction and wear tests that use friction force microscopy (FFM), the wear debris transfer to the tip apex that changes tip radius is a crucial issue that influences the friction and wear performances of films and coatings with nanoscale thicknesses. In this study, FFM tests are performed for bilayer $MoS_2$ film to obtain a better understanding of how geometrical and chemical changes of tip apex influence the friction and wear properties of nanoscale molecular layers. The critical load can be estimated from the test results based on the clear distinction of the failure area. Scanning electron microscopy and energy-dispersive spectroscopy are employed to measure and observe the geometrical and chemical changes of the tip apex. Under normal loads lower than 1000 nN, the reuse of tips enhances the friction and wear performance at the tip-sample interface as the contact pair changes with the increase of tip radius. Therefore, the reduction of contact pressure due to the increase of tip radius by the transfer of $MoS_2$ or Mo-dominant wear debris and the change of contact pairs from diamond/$MoS_2$ to partial $MoS_2$ or Mo/$MoS_2$ can explain the critical load increase that results from tip reuse. We suggest that the wear debris transfer to the tip apex should be considered when used tips are repeatedly employed to identify the tribological properties of ultra-thin films using FFM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11C
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• pp.1083-1090
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• 2005

This paper presents the design of a video encoder for the device of need TV-OUT function. The designed video encoder satisfies the standard conditions of International Telecommunication Union-Radiocommunication (ITU-R) BT.470. ITU-R BT.470 can be classified as NTSC, PAL or SECAM. NTSC and PAL use Amplitude Modulation (AM) to transmit color difference signals and SECAM uses Frequency Modulation (FM). SECAM must have an antic-cloche filter but the filter recommended by ITU-R BT.470 is not easy to design due to sharpness of the frequency response. So formerly the filter was designed as analog. This paper proposes that the filter is designed as digital and the special quality of the filter is transformed easy to design. And the modulation method is modified to be identical with the result required at standard. The encoder can control power consumption by output mode to apply mobile phone, mobile devices, etc. The proposed encoder is experimentally demonstrated with ALTERA FPGA APEX20KE EP20K1000EBC652-3 device and SAMSUNG LCD-TV.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.332-346
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• 2003

In this paper, a system which can compress and reconstruct the digital image was implemented using 2 dimensional DWT(Discrete Wavelet Transform). The proposed system consists of the FPGA board tocompress the image and the application software(S/W) to reconstruct it. First the FPGA receives the image from AID converter and compresses the image using wavelet transform. The compressed data is transferred into the PC using the PCI interface. The compressed image is reconstructed by an application S/W inside the PC. The image compressor can compress about 60 fields per second, in which the image format was NTSC YCbCr(4:2:2) and the image size was 640${\times}$240 pixels per field. The designed hardware mapped into one FPGA occupying 11,120 LAB (Logic Array Block) and 27,456 ESB(Embedded System Block) in APEX20KC EP20K1000B652-7. It globally uses 33MHz clock and the memory control part uses 100MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2A
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• pp.147-156
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• 2004

This paper presents an implementation and performance analysis of an access channel decoder which exploits a diversity gain due to the independent magnitude of received signals energy at each of antenna elements of a smart antenna BTS (Base-station Transceiver Subsystem) operating in CDMA2000 1X signal environment. Proposed access channel decoder consists of a searcher supporting 4 fingers, Walsh demodulator, and demodulator controller. They have been implemented with 5 of 1 million-gate FPGA's (Field Programmable Gate Array) Altera's APEX EP20K1000EBC652 and TMS320C6203 DSP (digital signal processing). The objective of the proposed access channel decoders is to enhance the data retrieval at co]1-site during the access period, for which the optimal weight vector of the smart antenna BTS is not available. Through experimental tests, we confirmed that the proposed access channel decoder exploitng the diversity technique outperforms the conventional one, which is based on a single antenna channel, in terms of detection probability of access probe, access channel failure probability, and $E_{b/}$ $N_{o}$ in Walsh demodulator.r.r.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.4
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• pp.207-213
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• 2006

This paper presents the design and implementation of a video processor for the device of need TV-OUT function. The designed video processor satisfies the standard conditions of ITU-R(International Telecommunication Union-Radiocommunication) BT.470. Also, in order to apply various digital device, we concentrate upon hardware complexity. ITU-R BT.470 can be classified as NTSC, PAL or SECAM. NTSC and PAL use QAM(Quardarature Amplitude Modulation) to transmit color difference signals and SECAM uses FM(Frequency Modulation). FM must have antic-cloche filter but filter recommended by ITU-R BT.470 is not easy to design due to sharpness of the frequency response. So this paper proposes that the special quality of anti-cloche filter is transformed easy to design and the modulation method is modified to be identical with the result required at standard. The processor can control power consumption by output mode to apply portable digital devices. The proposed processor is experimentally demonstrated with ALTERA FPGA APEX20KE EP20K1000EBC652-3 device and SAMSUNG LCD-TV.

• Journal of The Korean Society of Agricultural Engineers
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• v.46 no.6
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• pp.21-28
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• 2004

This study aims to investigate the effects of partially distributed loads on the dynamic behaviour of steel parabolic arches by using the elasto-plastic finite element model based on the Von Mises yield criteria and the Prandtl-Reuss How rule. For this purpose, the vertical and the radial load conditions were considered as a distributed loading and the loading range is varied from 40% to 100% of arch span. Normal arch and arch with initial deflection were studied. The initial deflection of arch was assumed by the sinusoidal motile of ${\omega}_i\;=\;{\\omega}_O$ sin ($n{\pi}x/L$). Several numerical examples were tested considering symmetric initial deflection when the maximum initial deflection at the apex is fixed as L/1000. The analysis resluts showed that the maximum deflection at the apex of arch was occurred when 70% of arch span was loaded. The maximum deflection at the quarter point of arch span was occurred when 50% of arch span was loaded. It is known that the optimal rise to span ratio between 0.2 and 0.3 when the vertical or radial distributed load is applied. It is verified that the influence of initial deflection of radial load case is more serious than that of vertical load case.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1241-1245
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• 2009

As FFT(Fast Fourier Transform) processor is used in OFDM(Orthogonal Frequency Division Multiplesing) system. According to increase requirement about mobility and broadband, Research about low power and low area FFT processor is needed. So research concern in reduction of memory size and complex multiplier is in progress. Increasing points of FFT increase memory area of FFT processor. Specially, SRU(Signal Reordering Unit) has the most memory in FFT processor. In this paper, we propose a reduced method of memory size of SRU in FFT processor. SRU of 64, 1024 point FFT processor performed implementation by VerilogHDL coding and it verified by simulation. We select the APEX20KE family EP20k1000EPC672-3 device of Altera Corps. SRU implementation is performed by synthesis of Quartus Tool. The bits of data size decide by 24bits that is 12bits from real, imaginary number respectively. It is shown that, the proposed SRU of 64point and 1024point achieve more than 28%, 24% area reduction respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.511-516
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• 2006

In this raper, we propose the Sequentiel Couleur Avec Memoire or Sequential Color with Memory (SECAM) video encoder system using modified anti-cloche filters and the SECAM video decoder system using a band pass filter (BPF) and an error-free square root. The SECAM encoder requires an anti-cloche filter recommended by International Telecommunication Union-Recommendation (ITU-R) Broadcasting service Television (BT) 470. However, the design of the anti-cloche filter is difficult because the frequency response of the anti-cloche filter is very sharp around rejection-frequency area. So, we convert the filter into a hish pass filter (HPF) by shifting the rejection frequency of 4.286MHz to 0Hz frequency. The design of HPF becomes very easy, compared to that of the anti-cloche filter. The proposed decoder also uses an error-free square root, two differentiators and trigonometric functions to extract color-component information of Db and Dr accurately from frequency modulation (FM) signals in SECAM systems. Also, the BPF in decoder it used for removing color noise in chrominance and dividing CVBS into chrominance and luminance. The proposed systems are experimentally demonstrated with Altera FPGA APEX20KE EP20K1000EBC652-3 device and TV sets.