• 제목/요약/키워드: AI chip

검색결과 37건 처리시간 0.017초

AB9: A neural processor for inference acceleration

  • Cho, Yong Cheol Peter;Chung, Jaehoon;Yang, Jeongmin;Lyuh, Chun-Gi;Kim, HyunMi;Kim, Chan;Ham, Je-seok;Choi, Minseok;Shin, Kyoungseon;Han, Jinho;Kwon, Youngsu
    • ETRI Journal
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    • 제42권4호
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    • pp.491-504
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    • 2020
  • We present AB9, a neural processor for inference acceleration. AB9 consists of a systolic tensor core (STC) neural network accelerator designed to accelerate artificial intelligence applications by exploiting the data reuse and parallelism characteristics inherent in neural networks while providing fast access to large on-chip memory. Complementing the hardware is an intuitive and user-friendly development environment that includes a simulator and an implementation flow that provides a high degree of programmability with a short development time. Along with a 40-TFLOP STC that includes 32k arithmetic units and over 36 MB of on-chip SRAM, our baseline implementation of AB9 consists of a 1-GHz quad-core setup with other various industry-standard peripheral intellectual properties. The acceleration performance and power efficiency were evaluated using YOLOv2, and the results show that AB9 has superior performance and power efficiency to that of a general-purpose graphics processing unit implementation. AB9 has been taped out in the TSMC 28-nm process with a chip size of 17 × 23 ㎟. Delivery is expected later this year.

자율주행시 안전을 위한 AI와 연계 시스템 적용연구 (A Study on the Application of AI and Linkage System for Safety in the Autonomous Driving)

  • 서대성
    • 한국융합학회논문지
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    • 제10권11호
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    • pp.95-100
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    • 2019
  • 본 논문은 자율 주행차량의 운행과 더불어 기존 차량 사고 방지를 위한 차량 간 통신 기술, 자율주행 기술, 브레이크 자동 제어 기술, 인공지능 기술 등이 널리 개발되고 있다. 차량 사고 발생이 일어나더라도 사망이나 부상을 최소화하기 위한 각종 기술들의 안전성의 상용화에 있다. 본 논문의 경우 자율주행 차량시, 안전성 확보연구이다. 이는 일반적인 저전력 근거리 무선 통신용 칩 신호나 초소형 도로 AI 장착 등의 공간적 요소에 따라 판별한다. 반면 본 논문은 상기 전자 칩의 신호를 읽는 데에서 생체 전자 칩까지의 "감지영역 내 체류 시간인식, 민감도"까지 체크하여 승차한 안전의 신뢰성을 높인다. 실제 세계 각국의 신뢰성을 실증한 결과로서, 안전성면에서 탑승객 전원의 안전 자율 시스템을 유도한다. 무인 자율차량 탑승과 상용화는 가까운 미래에 도로위 IoT의 AI 시스템과 생체 칩(Verification emotion + Chip)으로의 연계성면에서 그 진보성의 실증결과, 세계 각국의 안전 기술신뢰성은 더욱 부각된다.

Al 스크랩으로부터 금속회수에 관한 연구 (A Study of the Metal Recovery from the Aluminium Scrap)

  • 김준수;임병모;윤의박
    • 자원리싸이클링
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    • 제4권1호
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    • pp.25-30
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    • 1995
  • 본 연구에서는 Al 스크랩으로부터 재생지금 제조시 시료의 예비처리, 용제첨가 및 용해분위기가 Al 회수율에 미치는 영향을 조사하였다. 실험결과에 따르면 Al 드로스는 용탕표면에서의 산화반응에 의해 발생하였다. 예비처리의 영향에 다르면 탈지하지 않고 압착한 칩 bale 시료의 경우에는 압착하지 않은 칩 시료에 비해 약 14%의 회수율이 증가하였으며, Al seed 용해공법을 채택하는 경우에는 탈지하지 않고 단지 세편과 압착만을 행하여도 97%의 높은 회수율을 얻을 수 있었다. Al 스크랩 용해시 7wt%까지 첨가된 염에 의해 회수율은 최대 95%까지 증대되었으며, 탄소 및 질소분위기에서도 역시 회수율은 증가하였으나, 염과 탄소의 혼합분 첨가시 과잉 첨가된 탄소는 오히려 회수율을 감소시켰다.

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8.2-GHz band radar RFICs for an 8 × 8 phased-array FMCW receiver developed with 65-nm CMOS technology

  • Han, Seon-Ho;Koo, Bon-Tae
    • ETRI Journal
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    • 제42권6호
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    • pp.943-950
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    • 2020
  • We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

Examining the Generative Artificial Intelligence Landscape: Current Status and Policy Strategies

  • Hyoung-Goo Kang;Ahram Moon;Seongmin Jeon
    • Asia pacific journal of information systems
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    • 제34권1호
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    • pp.150-190
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    • 2024
  • This article proposes a framework to elucidate the structural dynamics of the generative AI ecosystem. It also outlines the practical application of this proposed framework through illustrative policies, with a specific emphasis on the development of the Korean generative AI ecosystem and its implications of platform strategies at AI platform-squared. We propose a comprehensive classification scheme within generative AI ecosystems, including app builders, technology partners, app stores, foundational AI models operating as operating systems, cloud services, and chip manufacturers. The market competitiveness for both app builders and technology partners will be highly contingent on their ability to effectively navigate the customer decision journey (CDJ) while offering localized services that fill the gaps left by foundational models. The strategically important platform of platforms in the generative AI ecosystem (i.e., AI platform-squared) is constituted by app stores, foundational AIs as operating systems, and cloud services. A few companies, primarily in the U.S. and China, are projected to dominate this AI platform squared, and consequently, they are likely to become the primary targets of non-market strategies by diverse governments and communities. Korea still has chances in AI platform-squared, but the window of opportunities is narrowing. A cautious approach is necessary when considering potential regulations for domestic large AI models and platforms. Hastily importing foreign regulatory frameworks and non-market strategies, such as those from Europe, could overlook the essential hierarchical structure that our framework underscores. Our study suggests a clear strategic pathway for Korea to emerge as a generative AI powerhouse. As one of the few countries boasting significant companies within the foundational AI models (which need to collaborate with each other) and chip manufacturing sectors, it is vital for Korea to leverage its unique position and strategically penetrate the platform-squared segment-app stores, operating systems, and cloud services. Given the potential network effects and winner-takes-all dynamics in AI platform-squared, this endeavor is of immediate urgency. To facilitate this transition, it is recommended that the government implement promotional policies that strategically nurture these AI platform-squared, rather than restrict them through regulations and stakeholder pressures.

차량용 반도체 공급망 생태계 (Supply Chain Ecosystem of Automotive Chip)

  • 전황수;김현탁;노태문
    • 전자통신동향분석
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    • 제36권3호
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    • pp.1-11
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    • 2021
  • In this study, we analyze the automotive chip ecosystem that recently caused the global supply shortage, and attempt to derive policy implications for us from the conclusion. Automotive chips are critical parts that control various systems so that a vehicle can drive itself or operate with electricity. The current shortage in supply and demand for automotive chips is due to the inconsistency between supply and demand between automotive chip companies and car manufacturers. To promote the automotive chip industry, new investment incentives, tax cuts, and human resource training are needed.

합성곱 신경망 기반의 인공지능 FPGA 칩 구현 (A Realization of CNN-based FPGA Chip for AI (Artificial Intelligence) Applications)

  • 윤영
    • 한국항해항만학회:학술대회논문집
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    • 한국항해항만학회 2022년도 추계학술대회
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    • pp.388-389
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    • 2022
  • 최근 인공지능 분야는 자율주행, 로봇 및 스마트 통신등 다양한 분야에 응용되고 있다. 현재의 인공지능 응용분야는 파이썬을 기반으로 한 tensor flow를 이용하는 소프트웨어 방식을 이용하고 있으며, 프로세서로는 PC의 그래픽 카드 내부에 존재하는 GPU (Graphics Processing Unit)를 이용하고 있다. 그러나 GPU 기반의 소프트웨어 방식은 하드웨어를 변경할 수 없다는 문제점을 가지고 있다. 이러한 문제점으로 인해 높은 수준의 판단이나 작업을 요구하는 경우에는 이에 적합한 높은 사양의 GPU가 필요하며, 이러한 경우에는 인공지능 작업을 처리하는 그래픽 카드로 교체해야 한다. 이러한 문제점을 해결하기 위해 본 연구에서는 HDL (Hardware Description Language)을 이용하여 반도체 내부의 회로를 변경할 수 있는 FPGA (Field Programmable Gate Array)를 기반으로 한 신경망 회로를 이용하여 합성곱 신경망 기반의 인공지능 시스템을 구현하고자 한다.

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An impulse radio (IR) radar SoC for through-the-wall human-detection applications

  • Park, Piljae;Kim, Sungdo;Koo, Bontae
    • ETRI Journal
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    • 제42권4호
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    • pp.480-490
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    • 2020
  • More than 42 000 fires occur nationwide and cause over 2500 casualties every year. There is a lack of specialized equipment, and rescue operations are conducted with a minimal number of apparatuses. Through-the-wall radars (TTWRs) can improve the rescue efficiency, particularly under limited visibility due to smoke, walls, and collapsed debris. To overcome detection challenges and maintain a small-form factor, a TTWR system-on-chip (SoC) and its architecture have been proposed. Additive reception based on coherent clocks and reconfigurability can fulfill the TTWR demands. A clock-based single-chip infrared radar transceiver with embedded control logic is implemented using a 130-nm complementary metal oxide semiconductor. Clock signals drive the radar operation. Signal-to-noise ratio enhancements are achieved using the repetitive coherent clock schemes. The hand-held prototype radar that uses the TTWR SoC operates in real time, allowing seamless data capture, processing, and display of the target information. The prototype is tested under various pseudo-disaster conditions. The test standards and methods, developed along with the system, are also presented.

A 0.9-V human body communication receiver using a dummy electrode and clock phase inversion scheme

  • Oh, Kwang-Il;Kim, Sung-Eun;Kang, Taewook;Kim, Hyuk;Lim, In-Gi;Park, Mi-Jeong;Lee, Jae-Jin;Park, Hyung-Il
    • ETRI Journal
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    • 제44권5호
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    • pp.859-874
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    • 2022
  • This paper presents a low-power and lightweight human body communication (HBC) receiver with an embedded dummy electrode for improved signal acquisition. The clock data recovery (CDR) circuit in the receiver operates with a low supply voltage and utilizes a clock phase inversion scheme. The receiver is equipped with a main electrode and dummy electrode that strengthen the capacitive-coupled signal at the receiver frontend. The receiver CDR circuit exploits a clock inversion scheme to allow 0.9-V operation while achieving a shorter lock time than at 3.3-V operation. In experiments, a receiver chip fabricated using 130-nm complementary metal-oxide-semiconductor technology was demonstrated to successfully receive the transmitted signal when the transmitter and receiver are placed separately on each hand of the user while consuming only 4.98 mW at a 0.9-V supply voltage.

3D 칩 적층을 위한 하이브리드 본딩의 최근 기술 동향 (Recent Progress of Hybrid Bonding and Packaging Technology for 3D Chip Integration)

  • 정철화;정재필
    • 반도체디스플레이기술학회지
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    • 제22권4호
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    • pp.38-47
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    • 2023
  • Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

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