• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.653-656
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• 2013

TFTP(Trivial File Transfer Protocol)는 UDP(User Datagram Protocol) 기반의 파일 전송 프로토콜이다. TFTP는 프로토콜 구조가 단순하여 작은 크기의 데이터를 빠른 속도로 전송할 때 사용된다. 하지만 TFTP는 보안 기능을 지원하지 않기 때문에 데이터 노출의 위험이 있다. 본 논문에서는 Diffie-Hellman 키 교환 방식과 AES-CBC(Advanced Encryption Standard-Cipher Block Chaining) 암호화 방식을 이용하여 TFTP 프로토콜에 보안 기능을 추가하였다. Diffie-Hellman 키 교환 방식을 이용하여 두 사용자 간에 비밀 키를 공유하도록 하였고, AES-CBC 암호화를 지원하여 기밀성을 제공하도록 하였다. 수신된 데이터는 암호화 과정의 역으로 복호화를 수행하였다. WireShark 프로그램을 통하여 암호화된 데이터가 전송 되는 것을 확인하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.798-803
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.1li wireless LAN security. To maximize its performance, two AES cores ate used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining) mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about $20\%$ compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 13,360 gates, and the estimated throughput is about 168 Mbps at 54-MHz clock frequency. The functionality of the CCMP core is verified by Excalibur SoC implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.367-370
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.11i wireless LAN security. To maximize its performance, two AES cores are used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining)mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about 25% compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 15,450 gates, and the estimated throughput is about 128 Mbps at 50-MHz clock frequency). The functionality of the CCMP core is verified by Excalibur SoC implementation.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.2
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• pp.133-139
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• 2017

Vehicles have increasingly evolved and become intelligent with convergence of information and communications technologies (ICT). Vehicle communications (VC) has become one of the major necessities for intelligent vehicles. However, VC suffers from serious security problems that hinder its commercialization. Hence, the IEEE 1609 Wireless Access Vehicular Environment (WAVE) protocol defines a security service for VC. This service includes Advanced Encryption Standard-Counter with CBC-MAC (AES-CCM) for data encryption in VC. A high-speed AES-CCM crypto module is necessary, because VC requires a fast communication rate between vehicles. In this study, we propose and implement an efficient AES-CCM hardware architecture for high-speed VC. First, we propose a 32-bit substitution table (S_Box) to reduce the AES module latency. Second, we employ key box register files to save key expansion results. Third, we save the input and processed data to internal register files for secure encryption and to secure data from external attacks. Finally, we design a parallel architecture for both cipher block chaining message authentication code (CBC-MAC) and the counter module in AES-CCM to improve performance. For implementation of the field programmable gate array (FPGA) hardware, we use a Xilinx Virtex-5 FPGA chip. The entire operation of the AES-CCM module is validated by timing simulations in Xilinx ISE at a speed of 166.2 MHz.