• Journal of the Korea Computer Industry Society
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• v.10 no.3
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• pp.105-114
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• 2009

In this paper a modified Feistel network 128 bit block cipher algorithm is proposed. The proposed algorithm has a 128, 196 or 256 bit key and it updates a selected 32 bit word from input value whole by deformed Feistel Network structure. Existing of such structural special quality is getting into block cipher algorithms and big distinction. The proposed block cipher algorithm shows much improved software speed compared with international standard block cipher algorithm AES and domestic standard block cipher algorithm SEED and ARIA. It may be utilized much in same field coming smart card that must perform in limited environment if use these special quality.

• The KIPS Transactions:PartC
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• v.8C no.3
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• pp.277-286
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• 2001

본 논문에서는 미국 국립표준기술연구소 차세대 표준 암호 알고리듬으로 선정한 Rijndael 암호 알고리듬과 안정성과 성능에서 인정을 받은 Twofish 암호 알고리듬을 ALTERA FPGA를 사용하여 하드웨어로 구현한다. 두가지 알고리듬에 대해 키스케쥴링과 인터페이스를 하드웨어에 포함시켜 구현한다. 알고리듬의 효율적인 동작을 위해 키스케쥴링을 포함하면서도 구현된 회로의 크기가 크게 증가하지 않으며, 데이터의 암호/복호화 처리 속도가 향상됨을 알 수 있다. 주어진 128-비트 대칭키에 대하여, 구현된 Rijndael 암호 알고리듬은 11개의 클럭 만에 키스케쥴링을 완료하며, 구현된 Twofish 암호 알고리듬은 21개의 클럭 만에 키스케쥴링을 완료한다. 128-비트 입력 데이터가 주어졌을 때, Rijndael의 경우, 10개의 클럭 만에 주어진 데이터의 암호/복호화를 수행하고, Twofish는 16개의 클럭 만에 암호/복호화를 수행한다. 또한, Rijndael은 336.8Mbps의 데이터 처리속도를 보이고, Twofish는 121.2Mbps의 성능을 보임을 알 수 있다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.5
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• pp.997-1006
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• 2019

To overcome the difficulties and inefficiencies of the existing power analysis attack, we try to extract the secret key embedded in a cryptographic device using attack model based on MLP(Multi-Layer Perceptron) method. The target of our proposed power analysis attack is the AES-128 encryption module implemented on an 8-bit processor XMEGA128. We use the divide-and-conquer method in bytes to recover the whole 16 bytes secret key. As a result, the MLP-based power analysis attack can extract the secret key with the accuracy of 89.51%. Additionally, this MLP model has the 94.51% accuracy when the pre-processing method on power traces is applied. Compared to the machine leaning-based model SVM(Support Vector Machine), we show that the MLP can be a outstanding method in power analysis attacks due to excellent ability for feature extraction.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.6
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• pp.77-87
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• 2001

This paper describes a design of cryptographic processor that implements the Rijndael cipher algorithm, the Advanced Encryption Standard algorithm. It can execute both encryption and decryption, and supports only 128-bit block and 128-bit keys. As the processor is implemented only one round, it must iterate 11 times to perform an encryption/decryption. We implemented the ByteSub and InvByteSub transformation using the algorithm for minimizing the increase of area which is caused by different encryption and decryption. It could reduce the memory size by half than implementing, with only ROM. We estimate that the cryptographic processor consists of about 15,000 gates, 32K-bit ROM and 1408-bit RAM, and has a throughput of 1.28 Gbps at 110 MHz clock based on Samsung 0.5um CMOS standard cell library. To our knowledge, this offers more reduced memory size compared to previously reported implementations with the same performance.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.39-49
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• 2008

AEA and ARIA are next generation standard block cipher of US and Korea, respectively, and these algorithms are used in various fields including smart cards, electronic passport, and etc. This paper addresses the first efficient unified hardware architecture of AES and ARIA, and shows the implementation results with 0.25um CMOS library. We designed shared S-boxes based on composite filed arithmetic for both algorithms, and also extracted common terms of the permutation matrices of both algorithms. With the $0.25-{\mu}m$ CMOS technology, our processor occupies 19,056 gate counts which is 32% decreased size from discrete implementations, and it uses 11 clock cycles and 16 cycles for AES and ARIA encryption, which shows 720 and 1,047 Mbps, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.4
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• pp.805-810
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• 2012

Recently, applications range of NFC is widening by popularization of smartphone. Expansion of NFC means generalization of electronic payments systems. So security of NFC is very important. AES-128 is safe cryptographic technique for NFC now in use. But, the more range of applications increases, the more safe cryptographic techniques are necessary. In this paper, we propose the safe method is unaffected by the development of NFC. Proposed A-NFC scheme, adding the authentication of asymmetric cryptographic, is easy to apply for NFC and NFC-USIM chipsets, and it can adapt to the general NFC environment.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.3
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• pp.105-108
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• 2015

In this paper, we propose a differential fault analysis on symmetric SPN block cipher with bitslice involution S-box in 2011. The target block cipher was designed using AES block cipher and has advantage about restricted hardware and software environment using the same structure in encryption and decryption. Therefore, the target block cipher must be secure for the side-channel attacks. However, to recover the 128-bit secret key of the targer block cipher, this attack requires only one random byte fault and an exhausted search of $2^8$. This is the first known cryptanalytic result on the target block cipher.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.6
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• pp.1117-1127
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• 2014

Differential Fault Analysis(DFA) is widely known for one of the most powerful method for analyzing block cipher. it is applicable to block cipher such as DES, AES, ARIA, SEED, and lightweight block cipher such as PRESENT, HIGHT. In this paper, we introduce a differential fault analysis on the lightweight block cipher LEA for the first time. we use 300 chosen fault injection ciphertexts to recover 128-bit master key. As a result of our attack, we found a full master key within an average of 40 minutes on a standard PC environment.

• Convergence Security Journal
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• v.24 no.1
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• pp.69-76
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• 2024

The white-box implementation is a cryptographic technique used to protect the secret key of a cryptographic system. It is primarily employed for digital rights management for music and videos. Since 2002, numerous white-box implementations have been developed to ensure secure digital rights management. These have been applied to AES and DES. ARIA, a 128-bit block cipher with an involution substitution and permutation network (SPN), was selected as a South Korean standard in 2004. In this paper, we propose the first white-box ARIA implementation. Our implementation consists of 7,696 lookup tables, with a total size of 1,984 KB. We demonstrate that it also has considerable white-box diversity and white-box ambiguity from a security perspective.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.6
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• pp.1319-1326
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• 2015

The symmetric key encryption algorithms, such as the AES or the ARIA, generate round keys by the key expansion mechanism. While the algorithm is executed, key expansion mechanism emits information about the secret key by the power consumption. The vulnerability exists that can reduce significantly the candidate of the secret key by the simple power analysis attack using a small number of the power traces. Therefore, we'll have to study about the attack and the countermeasure to prevent information leakage. While a simple power analysis attack on the AES key expansion has been studied since 2002, ARIA is insufficient. This paper presents a simple power analysis attack on 8-bit implementations of the ARIA-128 key expansion. The presented attack efficiently utilizes this information leakage to substantially reduce the key space that needs to be considered in a brute-force search for the secret key. We show that ARIA is vulnerable to a SPA attack based on hamming weight leakage.