• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1491-1500
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• 2001

본 논문에서는 AES Rijndael 암호 알고리즘을 구현하는 암호 프로세서를 설계하였다. 하드웨어 공유를 통해 면적을 감소시키기 위해 1라운드 동작을 2개의 부분 라운드로 나누고 각 부분 라운드를 4 클록으로 구현하였다. 라운드 당 평균 5 클록의 연산 효율을 만들기 위해 인접한 라운드간에 부분 라운드 라이프라인 동작 기법을 적용하고, 키 설정 오버헤드 시간을 배제하기 위해, 암호 및 복호 동작의 라운드 키를 온라인 계산 기법을 사용하여 생성하였다. 그리고 다양한 응용 분야에 적용하기 위해, 128, 192, 256 비트의 3가지 암호 키를 모두 지원할 수 있도록 하였다. 설계된 암호 프로세서는 약 36,000개의 게이트로 구성되며 0.25$\mu\textrm{m}$ CMOS 공정에서 약 200Mhz의 동작 주파수를 가지며, 키 길이가 128 비트인 AES-128 ECB 동작 모드에서 약 512 Mbps의 암.복호 율의 성능을 얻을 수 있었다.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.67 no.1
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• pp.9-14
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• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

• ETRI Journal
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• v.33 no.3
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• pp.434-442
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• 2011

This paper presents a practical differential fault analysis method for the faulty Advanced Encryption Standard (AES) with a reduced round by means of a semi-invasive fault injection. To verify our proposal, we implement the AES software on the ATmega128 microcontroller as recommended in the standard document FIPS 197. We reduce the number of rounds using a laser beam injection in the experiment. To deduce the initial round key, we perform an exhaustive search for possible key bytes associated with faulty ciphertexts. Based on the simulation result, our proposal extracts the AES 128-bit secret key in less than 10 hours with 10 pairs of plaintext and faulty ciphertext.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.15-25
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• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

• Journal of IKEEE
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• v.23 no.3
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• pp.971-977
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• 2019

This paper presents an experimental result showing the encryption and decryption times of the AES and LEA algorithms. AES and LEA algorithms are international and Korean standards for block ciphers, respectively. Through experiments, this paper investigates the applicability of the LEA algorithm for light weight IoT devices. In order to measure the encryption and decryption times, 256-bit and 128-bit secret keys were randomly generated for AES and LEA, respectively. Under our test environment using an Arduino microcontroller, the AES algorithm takes about 45ms for encryption and decryption processes, whereas the LEA algorithm takes about 4ms. Even though processing times of each algorithm may vary much under different implementation and test environments, this experimental result shows that the LEA algorithm can be applied to many light weight IoT devices for security goals.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.5
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• pp.67-77
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• 2006

Radio Frequency IDentification (RFID) will soon become an important technology in various industries. Therefore, security mechanisms for Rm systems are emerging crucial problems in RFID systems. In order to guarantee privacy and security, it is desirable to encrypt the transferred data with a strong crypto algorithm. In this paper, we present the ultra-light weight Advanced Encryption Standard (AES) processor which is suitable for RFID tags. The AES processor requires only 3,992 logic gates and is capable of both 128-bit encryption and decryption. The processor takes 446 clock cycles for encryption of a 128-bit data and 607 clock cycles for decryption. Therefore, it shows 55% improved result in encryption and 40% in decryption from previous cases.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1741-1748
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• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.599-602
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• 2014

FPGA상에 AES 복호화 코어를 FIPS-197사양에 기술된 AES 알고리즘의 복호화부분을 구현하였다. 키값의 길이는 128/192/256비트를 지원하며, 별도의 코어 로직은 FPGA의 6-input lookup table의 이점을 살리도록 설계되었으며, 이결과로 2000개의 lookup table만을 이용하여 256비트 키에서 3Gbps의 처리가 가능하게 되었다. 코어는 난수 및 FIPS-197, SP-800a와 AESAVS사양의 테스트 벡터를 통해서 검증하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1082-1088
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• 2005

Generating fast round key in AES Rijndael algorithm using three key sizes, such as 128, 192, and 256-bit keys is a critical factor to develop high throughput AES processors. In this paper, we propose on-the-fly round key generator which is applicable to the pipelined and non-pipelined AES processor in which cipher and decipher nodes must be implemented on a chip. The proposed round key generator has modular and area-and-time efficient structure implemented with simple connection of two key expander modules, such as key_exp_m and key_exp_s module. The round key generator for non-pipelined AES processor with support of three key lengths and cipher/decipher modes has about 7.8-ns delay time under 0.25um 2.5V CMOS standard cell library and consists of about 17,700 gates.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.427-433
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• 2002

This paper describes a design of cryptographic processor that implements the AES(Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation, the round block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.-V supply.