• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.3
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• pp.439-445
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• 2012

Since an attacker can extract secret key of cryptographic device by occurring an error during encryption operation, the fault injection attack have become a serious threat in cryptographic system. In this paper, we show that an attacker can retrieve the 128-bits secret key in AES implementation adopted iterative statement for round operations using fault injection attack. To verify the feasibility of our attack, we implement the AES algorithm on ATmega128 microcontroller and try to inject a fault using laser beam. As a result, we can extract 128-bits secret key by obtaining just two pairs of correct and faulty ciphertexts.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.1
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• pp.12-18
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• 2013

In 2012, Woosik Bae proposed a DAP3-RS(Design of Authentication Protocol for Privacy Protection in RFID Systems) using the hash function and AES(Advanced Encryption Standard) algorithm to hide Tag's identification and to generates variable data in every session. He argued that the DAP3-RS is safe from spoofing attack, replay attack, traffic analysis and etc. Also, the DAP3-RS resolved problem by fixed metaID of Hash-Lock protocol using AES algorithm. However, unlike his argue, attacker can pass authentication and traffic analysis using by same data and fixed hash value on the wireless. We proposed authentication protocol based on AES algorithm. Also, our protocol is secure and efficient in comparison with the DAP3-RS.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.4
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• pp.262-266
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• 2011

In high data-rate communication systems, encryption/decryption must be processed in high speed. In this paper, we implement CCM security mode which is the basis of security. Specifically, we combine CCM with AES block encryption algorithm in hardware. With the combination, we can carry out encryption/decryption as well as data transmission/reception simultaneously without reducing data-rate, and we keep low-power consumption with high speed by optimizing CCM block.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.285-288
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• 2001

In this paper a design of cryptographic coprocessor which implements AES Rijndael algorithm is described. To achieve average throughput of 1 round per 5 clocks, subround pipelined scheme is applied. To apply the coprocessor to various applications, three key sizes such as 128, 192, 256 bits are supported. The cryptographic coprocessor is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology and consists of about 36, 000 gates. Its peak performance is about 512 Mbps encryption or decryption rate under 200 Mhz clock frequency and 128-bit key ECB mode(AES-128ECB).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.627-628
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• 2010

S. Chow proposes white-box cryptography mechanism of AES algorithm(WBC-AES) in 2002. WBC mechanism is implementation method which is resistant to white-box attack. We describe the WBC-AES and contents protection method using it.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2093-2099
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• 2016

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.

• KIISE Transactions on Computing Practices
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• v.22 no.7
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• pp.303-309
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• 2016

Recently, an increasing number of embedded processors such as ARM Mali begin to support GPGPU programming frameworks, such as OpenCL. Thus, GPGPU technologies that have been used in PC and server environments are beginning to be applied to the embedded systems. However, many embedded systems have different architectural characteristics compare to traditional PCs and low-power consumption and real-time performance are also important performance metrics in these systems. In this paper, we implement a parallel AES cryptographic algorithm for a modern embedded GPU using OpenCL, a standard parallel computing framework, and compare performance against various baselines. Experimental results show that the parallel GPU AES implementation can reduce the response time by about 1/150 and the energy consumption by approximately 1/290 compare to OpenMP implementation when 1000KB input data is applied. Furthermore, an additional 100 % performance improvement of the parallel AES algorithm was achieved by exploiting the characteristics of embedded GPUs such as removing copying data between GPU and host memory. Our results also demonstrate that higher performance improvement can be achieved with larger size of input data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.67-74
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• 2004

AES is frequently used as a symmetric cryptography algorithm for the Internet. Wireless embedded systems increasingly use more conventional wired network protocols. Hence, it is important to have low-cost implementations of AES for thor The basic architecture of AES unrolls oかy one full cipher round which uses 20 S-boxes together with the key scheduler and the algorithm repeatedly executes it. To reduce the implementation cost further, the folded architecture which uses only eight S-box units was studied in the recent years. In this paper, we will study a low-cost AES implementation for wireless communication technology based on the folded architecture. We first improve the folded architecture to avoid the sixteen bytes of additional state memory. Then, we implemented a single byte architecture where only one S-box unit is used for data encryption and key scheduling. It takes 352 clocks to finish a complete encryption. We found that the maximum clock frequency of its FPGA implementation reaches about 40 MHz. It can achieve about 13 Mbps which is enough for 3G wireless communication technology.

• Journal of KIISE
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• v.42 no.9
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• pp.1100-1108
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• 2015

Classes.dex, which is the executable file for android operation system, has Java bite code format, so that anyone can analyze and modify its source codes by using reverse engineering. Due to this characteristic, many android applications using classes.dex as executable file have been illegally copied and distributed, causing damage to the developers and software industry. To tackle such ill-intended behavior, this paper proposes a technique to encrypt classes.dex file using an AES(Advanced Encryption Standard) encryption algorithm and decrypts the applications encrypted in such a manner in order to prevent reverse engineering of the applications. To reinforce the file against reverse engineering attack, hash values that are obtained from substituting a hash equation through the combination of salt values, are used for the keys for encrypting and decrypting classes.dex. The experiments demonstrated that the proposed technique is effective in preventing the illegal duplication of classes.dex-based android applications and reverse engineering attack. As a result, the proposed technique can protect the source of an application and also prevent the spreading of malicious codes due to repackaging attack.