• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.549-550
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• 2008

This paper proposed and designed the modified flash analog-to-digital converter(ADC). The speed of new architecture is similar to conventional flash ADC but the die area consumption is much less due to reduce numbers of comparators. The circuits which are implemented in this paper is simulated with LT SPICE and layout with Electric tools of computer.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2023.05a
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• pp.184-185
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• 2023

육상의 원격제어자가 선박을 제어할 때 가상의 모형선박이 같이 조종되도록 하여, 운전상태의 확인을 도울수 있도록 하고, 시험운항시 에뮬레이터를 선박에 연결하여 원격운전데이터의 시각적 확인이 될수 있도록 하였다. 또한 이더넷의 디지털데이터가 아날로그로 변환된후 커넥터로 케이블을 연결할수 있도록 하여, 아날로그 인터페이스를 가진 선박의 장비가 제어가 될수 있는 예시를 보여준다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.1023-1026
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• 2005

본 논문에서는 SDR(Software Defined Radio) 시스템을 위한 Digital IF(Intermediate Frequency) Up/Down 변환기를 설계하고 성능을 평가하였다. 설계한 시스템은 AD 변환부, DA 변환부 및 Up-Down conversion 기능을 수행하는 FPGA로 구성된다. AD 변환부는 Analog Device 사의 AD6645를 사용하였으며, DA 변환부는 Analog Device 사의 AD9775를 사용하였다. Up-Down conversion 기능을 수행하는 FPGA부는 샘플된 IF 입력을 혼합기와 NCO에 의해 기저대역(DC)으로 다운 시키는 역할을 하며, 14bit의 기저대역(DC) 신호를 혼합기와 NCO에 의해 IF 출력으로 올려주는 역할을 한다. 이러한 설계는 기존의 아날로그 헤테로다인 방식에 비하여 높은 유연성 및 우수한 성능 향상을 보여준다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.804-807
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• 2005

Design Up/Down converters which use Digital IF(Intermediate Frequency) techniques from the present paper, against hereupon performance the criticism. The reason which uses Digital IF techniques is configured of passive elements and the positions IF frequency domains are fixed and they do not use in the position one frequency but, the external fringe land of the board which comes to be configured with Digital IF without from the communication frequency domain which is various there to be a flexibility, the use was under possibility. Like this configuration compares in analog Heterodyne mode of existing and it has the performance upgrade which is excellent it shows a high flexibility.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.961-965
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• 2006

Design Up/Down converters which use Digital IF( Intermediate Frequency) techniques from the present paper, against hereupon performance the criticism. The reason which uses Digital IF techniques is configured of passive elements and the position If frequency domains are fixed and they do not use in the position one frequency but, the external fringe land of the board which comes to be configured with Digital IF without from the communication frequency domain which is various there to be a flexibility, the use was under possibility. Like this configuration compares in analog Heterodyne mode of existing and it has the performance upgrade which is excellent it shows a high flexibility.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1014-1015
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• 2015

본 논문은 MLCC (Multi-Layer Ceramic Capacitor) 시험용 전원 장치의 설계에 대해 기술 하였다. 개발된 전원 장치의 정격 출력 전압과 전류는 600V / 2A이며 경부하에서 중부하까지 200mV이하의 고 정밀도를 가진다. 전원 장치의 토플로지는 2-스위치 플라이백 컨버터를 인터리브시켜 고 전력/고 시스템 주파수가 가능하도록 구성했다. 출력 필터와 시스템 제어기를 설계하여 전압 리플과 노이즈를 감쇠시키고 시스템 안정도를 높였다. 특히 16bit AD변환기를 이용하여 제어 변수를 받아, DSP(TI사(社) TMS320F28335)로 정전압(CC) / 정전류(CV) 모드 제어를 보다 정밀하게 하였다. 최종적으로 시뮬레이션과 실험을 통해 고 정밀 전압의 전원 장치 설계의 타당성을 확인 하였다.

• Journal of the Korean Society for Nondestructive Testing
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• v.26 no.2
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• pp.99-107
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• 2006

Magnetic nondestructive testing is very useful far detecting a crack on the surface or near of the surface of the ferromagnetic materials. The distribution of the magnetic flux leakage (DMFL) on a specimen has to be obtained quantitatively to evaluate the crack. The magnetic camera is proposed to obtain the DMFL at the large lift-off. The magnetic camera consists of a magnetic source, magnetic lens, analog to digital converters (ADCs), interface, and computer. The magnetic leakage fields or the distorted magnetic fields from the object, which are concentrated on the magnetic lens, are converted to analog electrical signals tv arrayed small magnetic sensors. These analog signals are converted to digital signals by the ADCs, and are stored, imaged, and processed by the interface and computer. However the magnetic camera has limitations with respect to converting and switching speed, full range and resolution, direct memory access (DMA), temporary storage speed and volume because common ADCs were used. Improved techniques, such as those that introduce the operational amplifier (OP-Amp), amplify the signal, reduce the connection line, and use the low pass filter (LPF) to increase the signal to noise ratio are necessary. This paper proposes the exclusive embedded ADC including OP-Amp, LPF, microprocessor and DMA circuit for the magnetic camera to satisfy the conditions mentioned above.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.2
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• pp.63-70
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• 2003

In this paper, an MFC (Mass Flow Controller) which is widely used in many semiconductor manufacturing processes for controlling the mass flow rate of a gas is designed and implemented using the PIC 16F876 of Microchip, Inc. The MFC implemented in this thesis has the form of hybrid-type, i.e., the mixed-type of the analog-type MFC, which has many problems such as low accurary, and digital-type MFC, which use an expensive DSP (Digital Signal Processor) and an ADC (Analog to Digital Convertor) with high precision. The MFC is consists of the sensor unit, the control unit and the actuator unit, and it has used the automatic calibration algorithm and the reference table method for the improvement of the performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.579-584
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• 2008

A novel nondestructive testing (NDT) system, which is able to detect a crack with high speed and high spatial resolution, is urgently required for inspecting small cracks on express train wheels. This paper proposes an improved signal processing circuits, which uses the multiple amplifying circuits and the crack indicating pulse output system of the previous scan-type magnetic camera. Hall sensors are arrayed linearly, and the wheel is rotated with static speed in the vertical direction to sensor array direction. Each Hall voltages are amplified, converted and immediately operated by using, amplifying circuits, analog-to-digital converters and $\mu$-processor, respectively. The operated results, ${\partial}V_H/{\partial}t$, are compared with a standard value, which indicates a crack existence. If the ${\partial}V_H/{\partial}t$ is larger than standard value, the pulse signal is output, and indicates the existence of crack. The effectiveness of the novel method was verified by examine using cracks on the wheel specimen model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.35-42
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• 2004

A CMOS folding ADC with transistor differential pair folding circuit for low power consumption and high speed operation is presented in this paper. This paper explains the theory of transistor differential pair folding technique and many advantages compared with conventional folding and interpolation circuits. A ADC based on transistor differential pair folding circuit uses 16 fine comparators and 32 interpolation resistors. So it is possible to achieve low power consumption, high speed operation and small chip size. Design technology is based on fully standard 0.25${\mu}{\textrm}{m}$ double poly 2 metal n-well CMOS process. A power consumption is 45mW at 2.5V applied voltage and 250MHz sampling frequency. The INL and DNL are within $\pm$0.15LSB and $\pm$0.15LSB respectively. The SNDR is approximately 50dB at 10MHz input frequency.