• 대한전기학회논문지
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• 제33권9호
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• pp.347-354
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• 1984

This paper presents a method of improving the power factor and , the waveform of A.C line currents and the output waveforms of AC to DC fully bridge converter systems which is achieved by connecting CON I.II and CON III.IV in series and parallel. The basic principle of the CON I.II.III.IV's operation is simple and feasibility of thease converter is proved by experiments. CON I and CON III are constructed of natural commutation, CON II and CON IV are constructed of forced commutation. The experimental results show that the power factor and waveform of the source currents and the output waveforms are improved by the method of connecting converter in series and parallel and driving it in I, II, III, IV quadrant.

• 한국인터넷방송통신학회논문지
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• 제22권1호
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• pp.95-101
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• 2022

NP-난제로 알려진 양측 조립라인 균형문제는 주로 메타휴리스틱 방법들을 적용하여 해를 구하고 있다. 본 논문은 총 작업완료시간 W와 순환시간 c가 주어진 양측 조립라인의 선행순서도에서 좌측, 우측과 좌·우측 무관으로 공정들을 분류하고, 좌측과 우측 각각에 대해 M^* = ${\lceil}$W/c${\rceil}$개의 작업대에 T_i = c^* ± α < c, c^* = ${\lceil}$W/m^*${\rceil}$이 되도록 공정들을 할당하는 병렬군집 알고리즘을 제안하였다. 제안된 알고리즘을 4개의 실험데이터, 17개의 c에 적용한 결과, 기존의 메타휴리스틱 방법들에 비해 최소 작업대 수 m^*를 구하였으며, T_max < c로 순환시간을 단축하였다. 또한, 제안된 알고리즘은 휴리스틱 방법임에도 불구하고, 조립라인 효율성의 극대화와 작업자간 작업시간 편차를 최소화시킬 수 있었다.

• Journal of Power Electronics
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• 제13권4호
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• pp.507-515
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• 2013

This paper presents an isolated bidirectional dc/dc converter based on primary parallel isolated boost converter (PPIBC). This topology is an efficient solution in low voltage high power applications due to its ability to handle high currents in the low voltage side. In this paper, the converter has been modeled using non-ideal components and operated without any additional circuitry for startup using a digital soft-start procedure. Simulated and measured loop gains have been compared for the validity of the model. On-the-fly current direction change has been achieved with a prototype interconnecting two battery banks. A second prototype has been constructed and tested for supercapacitor operation in constant power charge mode.

• Progress in Superconductivity
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• 제5권1호
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• pp.45-49
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• 2003

We have designed and fabricated the single-layer high $T_{c}$ SQUID magnetometer consisting of a directly coupled grain boundary junction SQUID with an inductance of 100 pH and 16 nested parallel pickup coils with the outermost dimension of 8.8 mm ${\times}$ 8.8 mm. The magnetometer was formed from a YBCO thin film deposited on an STO(100) bicrystal substrate with a misorientation angle of $30^{\circ}$. The SQUID magnetometer was further improved by optimizing the multi-loop pickup coil design for use in unshielded environments. Typical characteristics of the dc SQUID magnetometer had a modulation voltage of 40 $\mu\textrm{V}$ and a white noise of $30fT/Hz^{1}$2/. The SQUID magnetometer exhibited a 1/f noise level at 10 Hz reduced by a factor of about 3 compared with that of the conventional solid type pickup coil magnetometers and a very stable flux locked loop operation in magnetically disturbed environments.s.

• 대한음성학회지:말소리
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• 제52호
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• pp.111-120
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• 2004

This paper focuses on the DSP implementation of an HMM-based speech recognizer that can handle several hundred words of vocabulary size as well as speaker independency. First, we develop an HMM-based speech recognition system on the PC that operates on the frame basis with parallel processing of feature extraction and Viterbi decoding to make the processing delay as small as possible. Many techniques such as linear discriminant analysis, state-based Gaussian selection, and phonetic tied mixture model are employed for reduction of computational burden and memory size. The system is then properly optimized and compiled on the TMS320C6711 DSP for real-time operation. The implemented system uses 486kbytes of memory for data and acoustic models, and 24.5 kbytes for program code. Maximum required time of 29.2 ms for processing a frame of 32 ms of speech validates real-time operation of the implemented system.

• Journal of Power Electronics
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• 제13권3호
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• pp.329-338
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• 2013

In this paper, the charging characteristics of series resonant type high voltage capacitor chargers considering the transformer stray capacitance have been studied. The principles of operation for the four operational modes and the mode changes for the four different switching frequency sections are explained and analyzed in the range of switching frequency below the resonant frequency. It is confirmed that the average charging currents derived from the above analysis results have non-linear characteristics in each of the four modes. The resonant current, resonant voltage, charging current, and charging time of this capacitor charger as variations of the switching frequency, series parallel capacitance ratio ($k=C_p/C_s$), and output voltage are calculated. From the calculation results, the advantages and disadvantages arising from the parallel connection of this stray capacitance are described. Some methods to minimize charging time of this capacitor charger are suggested. In addition, the results of a comparative test using two transformers whose stray capacitances are different are described. A 1.8 kJ/s prototype capacitor charger is assembled with a TI28335 DSP controller and a 40 kJ, 7 kV capacitor. The analysis results are verified by the experiment.

• 한국전산유체공학회지
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• 제17권4호
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• pp.1-8
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• 2012

During a reactor normal operation, two parallel 50% capacity cooling pumps circulate primary coolant to remove the fission reaction heat of the reactor through heat exchangers cold by a cooling tower. When one pump is failure, the other pump shall continuously circulate the coolant to remove the residual heat generated by the fuels loaded in the reactor after reactor shutdown. It is necessary to estimate how much flow rate will be supplied to remove the residual heat. We carried out a flow network analysis for the parallel primary pumps based on the piping network of the primary cooling system in HANARO. As result, it is estimated that the flow rate of one pump increased about 1.33 times the rated flow of one pump and was maintained within the limit of the cavitation critical flow.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.291-291
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• 2000

A vehicle driving simulator is a virtual reality device which a human being feels as if the one drives a vehicle actually. Driving Operation System acts as an interface between a driver and a driving simulator. This paper suggests the driving operation system for a driving simulator. This system consists of a controller, DC geared motor, MR brake, rotary encoders, steeping motor and bevel gear box. Reaction force and torque on the steering system were made by DC_Motor and MR_Brake. Reaction force and torque on the steering system were compare between real car and a driving simulator. The controller based on the 80C196KC micro processor that manage and transfer signal.

• 대한전자공학회논문지SP
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• 제39권3호
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• pp.49-57
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• 2002

본 논문에서는 TMS320C80 MVP(multimedia video processor)를 이용하여 영상 항법변수 추출 알고리듬을 실시간 구현하는 방법에 대해 연구하였다. 영상 항법변수 추출 알고리듬은 상대위치 추정과 절대위치 보정으로 이루어져 있으며, 절대위치 보정은 고해상도 항공영상과 IRS(Indian remote sensing) 위성영상 그리고 DEM(digital elevation model)을 이용한 방법이 있다. 이러한 알고리듬들을 수행하는 통합시스템을 MVP가 탑재된 DSP 보드로 실시간 구현하였다. 이를 위해 영상을 분할하여 병렬처리 함으로써 처리 시간을 줄였다. 모의 실험을 통해 실시간 처리가 가능함을 알 수 있었고, 추정오차 측면에서 성능을 평가하였다.

• 대한전자공학회논문지SD
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• 제44권9호
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• pp.59-70
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• 2007

본 논문에서는 휴대 정보기기 시스템에서 더욱 향상된 실시간 3D 그래픽 가속 능력을 갖는 SoC(System on a Chip) 구현을 위해 효과적인 T&L(Transform & Lighting) Processor 구조를 연구하였다. T&L 과정에 필요한 IP들을 설계하였으며, 이를 바탕으로 SoC Platform 기반으로 검증하였다. 설계된 T&L Processor는 24 bits 부동소수점 형식과 16 bits 고정소수점 형식을 적절하게 혼용하고 계산식의 병렬성을 최대한 활용하여 Transform 과정 연산과 Lighting 과정 연산의 지연시간을 균일하게 배분하여 Transform 과정만 처리할 때와 Lighting과 혼용으로 처리할 때 연산 속도의 차이가 없이 동작이 가능하다. 설계된 T&L Processor는 SoC 플랫폼을 이용하여 성능 측정 실험 및 검증을 하였고, Xilinx-Virtex4 FPGA에서 80 MHz의 동작 주파수를 확인하였고 초당 20M개의 정점(Vertex) 처리 성능을 확인하였다.