• The KIPS Transactions:PartD
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• v.11D no.2
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• pp.415-422
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• 2004

Automation systems improve the productivity of works which relate to product design, facilities management, fault processing and quality evaluation. In these systems, the description language for monitoring and control process is called new control language. These are five flow control languages : IL, ST, FBD, SFC and LD. IL and ST are based on left form. FBD, SFC and LD are based on graphic form. Generally, a software which monitors and controls a system is allowed to use just one flow control language. It is impossible to use more than two languages for simulation in the same system environment. In this paper, we analyzed the characteristics of flow control languages and the process of programming in the legacy system. In addition, for the Integrated processing of languages, we propose Extended ST based on the high-level ST language. Based on this research, we implement a graphical language editor and EST-IL convertor. The graphical language editor makes sequence rules, and converts graphical language into EST. EST-IL convertor has a function to convert EST into IL which is similar to assembly language. As the result of this paper, we present a scheme which integrates all the flow control language processing based on IL.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.168-170
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• 2008

한글 상호(商號) 로마자 변환기는 한글로 만들어진 상호를 로마자로 자동 변환하는 시스템이다. 이 변환기는 기사용 로마자 상호명과 업종명, 그리고 표준 한글 로마자 변환 규칙에 의해 생성한 로마자를 조합하여 로마자 상호를 생성한다. 이때, 조합을 위한 알고리즘이 필요한데, 기존에 비슷한 용도에 사용되었던 stack 알고리즘을 적용할 경우 비효율적이다. 본 논문은 이를 대체할 새 알고리즘을 제안한다. 새 알고리즘은 기존 stack 알고리즘을 사용할 때에 비해 복잡도를 O(b^d)에서 O(b^*d)로 줄여 성능을 높인다.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.2
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• pp.111-117
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• 2004

The low-power design of the A/D converter is indispensable to achieve the compact bio-signal measuring device with long battery duration. In this paper, new decimation filter structure is proposed for the low-power design of the Sigma-Delta A/D converter in the bio-instruments. The proposed filter is based on the non-recursive structure of the CIC (Cascaded Integrator Comb) decimation filter in the Sigma-Delta A/D converter. By combining the CSD (Canonic Signed Digit) structure with common sub-expression sharing technique, the proposed decimation filter structure can significantly reduce the number of adders for implementation. For the fixed decimation factor of 16, the 15％ of power consumption saving is achieved in the proposed structure in comparison with that of the conventional polyphase CIC filter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.7 s.98
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• pp.681-689
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• 2005

This paper presents an ultra wide band(UWB) mixer using anti-parallel diode pair(APDP) with simulation and measurement results. The proposed mixer adopts the even-harmonic direct conversion mixing, which consists of a couple of filter, in-phase wilkinson power divider, wideband $45^{\circ}$ power divider, and APDP. The m mixer is operating over 3.1 to 4.8 GHz and producing quadrature(I/Q) outputs with a conversion loss of 18 dB and input third order intercept point($IIP_3$) of 15 dBm. I/Q outputs also have difference of about 0.5 dB and phase difference of ${\times}3^{\circ}$ and $P_{1dB}$ of 2 dBm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.963-969
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• 2008

This paper presents 6bit 100MHz Interpolation Flash Analog-to-Digital Converter, which can be applied to the Receiver of Wireless Tele-communication System. The 6bit 100MHz Flash Analog-to-Digital Converter simplifies and integrates S-R latch which multiplies as the resolution increases. Whereas the conventional NAND based S-R latch needed eight MOS transistors, this Converter was designed with only six, which makes the Dynamic Power Dissipation of the A/D Converter reduced up to 12.5%. The designed A/D Converter went through $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process to be a final product, and the final product has shown 282mW of power dissipation with 1.8V of Supply Voltage, 100MHz of conversion rate. And 35.027dBc, 31.253dB SFDR and 4.8bits, 4.2bits ENOB with 12.5MHz, 50MHz of each input frequency.

• The Transactions of the Korea Information Processing Society
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• v.2 no.1
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• pp.66-74
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• 1995

A 8-bit 15MHz CMOS subranging Analog-to-Digital converter for high-speed, low-power consumption applications is described. Subranging, 2 step flash, A/D converter used a new resistor string and a simple comparator architecture for the low power consumption and small chip area. Comparator exhibites 80dB loop gain, 50MHz conversion speed, 0.5mV offset and maximum error of voltage divider was 1mV. This Analog-to-Digital converter has been designed and fabricated in 1.2 m N-well CMOS technology. It consumed 150mW power at ＋5/-5V supply and delayed 65ns. The proposed Analog-to-Digital converter seems suitable for high- speed, low-power consumption, small area applications and one-chip mixed Analog- Digital system. Simulations are performed with PSPICE and a fabricated chip is tested.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.6 s.324
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• pp.1-7
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• 2004

The development of direct receiver techniques is expected to be a solution for future wideband or multi-band wireless systems based on software defined radio. In this Paper, we study the regeneration of I and Q signals for the SDR based direct conversion receiver, so that we can handle a wide bandwidth and maintain maximal flexibility in system utilization. After modeling the basic system considering the real wireless communication environment, and studying the impact of imperfect phase imbalance on the performance of a direct conversion receiver, we propose a suboptimal I and Q signal regeneration algorithm for the system. The proposed algerian regenerates I and Q signals using a real time early-late compensator which effectively estimates phase imbalances and gives feedback in a directreceiver. The proposed algorithm is shown to mitigate the impact of AWGN and improves performance especially at low SNR channel condition. According to the computer simulation, the BER performance of the proposed system is at least about 4 dB better than conventional systems under $45{\~}55$ degrees random phase errors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1120-1128
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• 2004

In this paper, we has designed and implemented Up-converter for K-band with high IMD3 performance using balanced power amplifier. It is consisted of PA module and, Local Oscillator module with reject Filter, mixer module and If block, and Up-converter has a local loop path to decide whether it operate or not and has the sensing port to inspect output power level. According to the power budget of designed Up-converter, K-band balanced power amplifier was fabricated by commercial MMIC. Measurement results of up-converter show about 40dB Gain, PldB of 29dBm and OIP3 was 38.25dBm, that is good performance compared to power budgets. We has adjusted gate voltage of MMIC to control more than 30 dB gain. This up-converter was used in transceiver for PTP and PTMP, and applied to digital communication system that use QAM and QPSK modulation.

• Journal of Biomedical Engineering Research
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• v.22 no.4
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• pp.339-347
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• 2001

• Journal of Satellite, Information and Communications
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• v.12 no.2
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• pp.61-64
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• 2017

A phase shifter is one of the key components that change the phase of an individual antenna in millimeter-wave phased array system. This paper presents a low-loss phase shifter design with two parallel 2-state amplifiers. To get the same gain of $0^{\circ}/180^{\circ}$ each state, delay lines are in the middle of each stage of the 2-Stage amplifiers. Normally, when adding AMPs in parallel, a power combiner/divider such as Wilkinson Power Combiner/Divider is added, but they are directly connected because it can cause added losses in silicon wafer. The measured data shows 12dB gain and 174-degree phase difference at 5GHz.