• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1025-1030
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• 2005

With the increasing use of multimedia technologies, image compression requires higher performance as well as new functionality. Specially, in the specific area of still image encoding, a new standard, JPEG2000 was developed. This paper proposed Set Partitioning Sorting Algorithm that uses a method to optimized selection of threshold from feature of wavelet transform coefficients and to removes sign bit in LL area on JPEG2000. Experimental results show the proposed algorithm achieves more improved bit rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.9B
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• pp.1329-1335
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• 2001

부호화 시스템의 성능 분석은 일반적으로 BER(Bit Error Rate)을 이용하여 이루어지는데, 많은 시간을 요하는 정확한 BER을 구하는 대신 근사치인 상한값(upper bound)을 이용하는 경우도 많다. 그러므로 실제 값과 가까운 BER 상한값을 구하는 것은 중요한 일이다. 터보부호의 경우 테일 비트(tail bit)에 의한 영향이 무시되는 블록 길이가 긴 경우[1]에 BER 상한값이 보고되었다. 그러나 테일 달기(tail terminating) 기법을 사용하면서 블록 길이가 짧을 경우 추가되는 테일 비트가 BER 상한값에 미치는 영향은 무시할 수 없게 된다. 따라서 본 논문에서는 테일비트를 고려한 터보부호의 BER 상한값 계산 방법을 제시한다. 그리고 테일 달기 기법보다 복잡하지만 테일 비트가 없으므로 블록 길이가 짧은 경우 효율적으로 사용될 수 있는 테일 물기(tail-biting) 기법을 이용하느 터보부호의 BER 상한값 계산 방법도 제시한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.269-272
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• 2005

For the efficient image encryption, we proposed the encryption algorithm using the chaotic function and elementary matrix operation defined on the bit plane decomposition. Though the chaotic encryption algorithm is faster than block encryption, it uses a real number computation. In this sense, we use the row and column operations on the bit-plane decomposed images combined with logistic function for the recursive rounding number, too.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.408-412
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• 1987

The designing method of the reflection and the loaded-line phase shifter is presented. Its phase shift is variable with changing of the stub parameters. In this paper, we design the 2-bit phase shifter which have 10\ulcornerand 90\ulcornerbit phase shift and analysi its characteristics. The experiments show 2d B max.insertion loss, 2.0max. input VSWR and 6\ulcornerphase error on 2.9-3.1GHz frequency range. They agree well with the theoretical results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.277-282
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• 2005

The arrangement of I-picture starting times of multiplexed variable bit .ate (VBR) MPEG videos may significantly affect the cell loss ratio (CLR) characteristics of the multiplexed traffic. This paper presents an efficient I-picture arrangement method which can minimize the CLR of the multiplexed traffic when multiple VBR MPEG videos are multiplexed onto a single constant bit rate link. In the proposed method, we use the probability that the arrival rate exceeds the link capacity as the measure for the CLR of the multiplexed traffic. Simulation results show that the proposed method can find more optimal arrangement than existing methods in respect of the CLR.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9A
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• pp.710-716
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• 2003

OFDM is a very attractive technique for achieving high-bit-rate data transmission and high spectrum efficiency. However one of disadvantages of OFDM signal is the high PAPR characteristic when multicarriers are added up coherently. In this paper, we propose an adaptive PTS scheme using two threshold levels for PAPR reduction and reducing the amount of PAPR calculations with clipping scheme. Simulation results show that it is almost same between average bit error rate performance of the proposed scheme and that of a conventional scheme. Also, we obtain a great performance gain in the amount of calculations compared to the conventional scheme. Therefore, proposed system has a good performance in data processing time in OFDM wireless communication systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.2027-2034
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• 1997

Frame relay is a fast packet switching technology that performs relaying and multiplexing frames with variable lengths over a wide area link at the T1 or E1 speed, by elminating error and flow control in the network. In frame relay networks, congestion control is typically performed through the rate enforcement with a discard eligibility (DE) bit, and the explicit negative feedback meachanisms using explicit congetion notification bits. In this paper, we consider the congestiong control scheme using the rate enforcement mechanism with DE bit for frame relay network. Assuming that each frame with exponentially distributed length arrives according to the Poission fashion, we can treat the frame relay switch as an M/M/1/K priority queueing system with pushout basis. We analyze and present the blocking probabilities and waiting time distributions of frames.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9B
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• pp.1616-1623
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• 1999

This paper describes error resilient coding scheme is added in WLL system and its application for robust low-bit rate still image transmission over power controlled W-CDA system Rayleigh fading channels. The baseline JPEG compressing methods are uses in image coding over wireless channel. The channel uses Reed-Solomon(RS) outer codes concatenated with convolutional inner codes, and truncated type I hybrid ARQ protocol based on the selective repeat strategy and the RS error detection capability. Simulation results are proved for the statistics of the frame-error bursts of the proposed system in comparison with conventional WLL system. it gains the 2 dB of the Eb/No in same BER.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.107-115
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• 2013

Smart appliances with multi-media and telecommunication equipments provide users complicated convenience functions. On the contrary, 8-bit controller-based low performance electronics still cannot afford such multimedia and telecommunication. If we find a way to have low-end electronics connected and provide complicated functions, they can be also made "smart". Fortunately, 8-bit controllers used in low-end appliances have UART, which can be connected to any of BlueTooth, Wi-Fi and ZigBee communication modules which can, in turn, communicate with smart devices. Any communication module can be attached to the low-end electronics due to the variety of smart devices' connectivity at the other side. Although the convenience functions seem complicated, they are actually macros in a script form composed of micro commands which implement the base functions of appliances. Since the kinds of the base functions are not that many, the low-end electronic appliances will become "smart" if their control program can be extended to execute sequentially the micro commands in any combination. Such simple innovation has not seen the world, until now due to the overhead of the additionally required hardware such as display devices and buttons. The high-quality display and touch screen functionalities of smart devices can replace the required hardware, and remove the overhead completely. In fact, the low-end appliances become smart as if an "evolution kit" is newly equipped.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1227-1234
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• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.