• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1393-1399
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• 1999

In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.

• Journal of the Korea Convergence Society
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• v.9 no.9
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• pp.1-8
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• 2018

It is a key role in leading and activating coding education as a process to solve problems creatively to produce and provide the educational contents on the basis of 3D printing. In this paper, we develop a variety of fusion contents to use 3D printing and 8bit MCU base control board which provides specific functions through Arduino. The developed control program conducts various packet monitoring more than ten times per a second, supporting intrinsically full duplex. In addition, communication protocol optimized in conveying a lot of information enables to control different contents. The contents produced with the control board and 3D printing are useful as a programming education tool to train the principle and the concept of coding.

• International journal of advanced smart convergence
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• v.9 no.1
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• pp.172-176
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• 2020

The implementation of a low phase noise voltage controlled oscillator (VCO) is important for the signal integrity of wireless communication terminal. A low phase noise wideband VCO for a wireless local area network (WLAN) application is presented in this paper. A 6-bit coarse tune capacitor bank (capbank) and a fine tune varactor are used in the VCO to cover the target band. The simulated oscillation frequency tuning range is from 8.6 to 11.6 GHz. The proposed VCO is desgned using 65 nm CMOS technology with a high quality (Q) factor bondwire inductor. The VCO is biased with 1.8 V VDD and shows 9.7 mA current consumption. The VCO exhibits a phase noise of -122.77 and -111.14 dBc/Hz at 1 MHz offset from 8.6 and 11.6 GHz carrier frequency, respectively. The calculated figure of merit(FOM) is -189 dBC/Hz at 1 MHz offset from 8.6 GHz carrier. The simulated results show that the proposed VCO performance satisfies the required specification of WLAN standard.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.4
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• pp.99-107
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• 2009

Visible Light Communication (VLC) is a promising wireless communication technology. It offers huge, worldwide available and free bandwidth without electro-magnetic interference, which makes it very attractive for RF-sensitive operating environments. We propose colored LED-based VLC system for hospital use which includes voice recognition system for operating the medical equipments. New Mr hlation Scheme based on the Light Color Space is suggested to overcome the effect of noise generated by background light. Different color space constellations for different symbol sizes are also suggested which would give better bit error rate performance. Finally, Slotted ALOHA or TDMA medium access control protocols are suggested for multi-user operations.

• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.4
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• pp.203-208
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• 2007

Ministry of Information and Communication is pushing for IT 839 strategy that has main points : 8 major service which can develop IT industry of Korea on the whole, 3 major infra, and 9 major new growth power. Of these, RFID/USN utilizing service is expected to exert a great influence the whole industry from field that is closely related with our life to national defense, supply, construction, transportation, physical distribution, manufacture, circulation, and service. In domestic case, departure of RFID/USN field is a little bit later than advanced nation's, and a technique difference between domestic field and that of advanced nation is about 2 years. In this situation, in order to develop middleware of various field gearing RFID Tag efficiently, we have to study about user interface and data analysis technique that is used in middleware commonly. This paper searches about WPF that appears in user interface field with up-to-date technique, and embodies 3 dimension visualization information system with WPF.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.197-204
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• 2010

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.67-74
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• 2016

This paper presents a novel multiple orthogonal subcarrier modulation based UHF band RFID communication system. In tag-to-reader communication, the demonstration system can deliver 1.6 Mbps through four subcarriers. To improve data rate while suppressing increase in circuit complexity, tag employs square-waves as the subcarriers and uses individual load modulators for each subcarrier. By using multiple orthogonal subcarrier based modulation, proposed communication system can be operated under existing UHF band RFID regulation. In reader, an OFDM demodulator is used. Since the tag backscatters the reader's CW carrier, carrier frequency offset compensation is not necessary in reader demodulator. Experimental results show that the demonstration system achieves a bit error rate of 10-5 at an Eb/N0 of 10.8 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2131-2139
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• 2014

In this paper, a binary-coded physical-layer network coding (PNC) is considered when high-order modulation techniques are used at source nodes in wireless communication environments. In the conventional PNC schemes, tight power control and phase compensation are required at a relay node. However, they may not be feasible in practical wireless communication environments. Thus, we do not assume the pre-equalization in this paper, and we only utilize the channel state information at receiver (CSIR). We propose a signal detection method for the binary-coded PNC with high-order modulation, such as QPSK and 16QAM, at the source nodes, while the conventional scheme only consider the BPSK at source nodes. We also analyze the bit-error performance of the proposed technique in both uncoded and coded cases.

• Journal of information and communication convergence engineering
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• v.5 no.2
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• pp.177-180
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• 2007

We compared CS-ACELP with QCELP speech coder in CDMA cellular under channel error environment and experimented performance with its measured value under channel error environment. Also, we specified the effective coding scheme to overcome. CS-ACELP speech coder using a LSP vector quantizer shows transparent speech quality from the results that SD is 0.92dB and outlier frames over 2dB is 2.9% in the BER 0.10% condition. CS-ACELP speech coder which is utilizing MA predictor shows better results on SVR and SEGSNR than QCELP speech coder(IS-96) adopting DPCM type predictor when bit error occurs from BER 0.01% to 0.50%.

• ETRI Journal
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• v.35 no.1
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• pp.1-6
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• 2013

In this paper, we present an implemented serial 40-Gb/s receiver optical subassembly (ROSA) module by employing a proposed TO-CAN package and flexible printed circuit board (FPCB). The TO-CAN package employs an L-shaped metal support to provide a straight line signal path between the TO-CAN package and the FPCB. In addition, the FPCB incorporates a signal line with an open stub to alleviate signal distortion owing to an impedance mismatch generated from the soldering pad attached to the main circuit board. The receiver sensitivity of the ROSA module measures below -9 dBm for 40 Gb/s at an extinction ratio of 7 dB and a bit error rate of $10^{-12}$.