• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.9
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• pp.738-745
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• 2012

This paper proposes an approximated soft decision demapping algorithm with low computational complexity for coded 4+12+16 amplitude phase shift keying (APSK) in an additive white Gaussian noise (AWGN) channel. To derive the proposed algorithm, we approximate the decision boundaries for 4+12+16 APSK symbols, and then decide the log likelihood ratio (LLR) value for each bit from the approximated decision boundaries. Although the proposed algorithm shows about 0.6~1.1dB degradation on the error performance compared with the conventional max-log algorithm, it gives a significant result in terms of the computational complexity.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.9
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• pp.907-915
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• 2002

In this paper, a compact digital phase shifter to be used an active phased array antenna system for satellite communications was proposed. The even and odd mode analysis for a given reflection-type phase shifter, which uses a folded hybrid coupler as a base element, was performed and the design parameters were derived. Also, to verify experimentally the electrical performances of the proposed structure, X-band 4-bit digital phase shifter was designed and fabricated using Teflon soft substrate $({\varepsilon}_r; =\;2.17)$. Its circuit size was less than 3.5 cm $\times$ 3.0 cm, and it exhibited at least 50 % size reduction as compared with the conventional unfolded configuration. The experimental results of the fabricated phase shifter showed that the average insertion loss and insertion loss variation were less than 3.5 dB, $\pm$ 0.6 dB within the operating band, 7.9 ~ 8.4 GHz, respectively. And, input and output return loss were more than 10 dB, respectively. Also, the phase response of the phase shifter showed 4-bit operation with $\pm$3$^{\circ}$ rms phase error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5C
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• pp.413-421
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• 2008

The paper derives asymptotic formulas for the MSE distortion and the signal-to-noise ratio of a mismatched fixed-rate minimum MSE Laplacian quantizer. These closed-form formulas are expressed in terms of the number N of quantization points, the mean displacement $\mu$, and the ratio $\rho$ of the standard deviation of the source to that for which the quantizer is optimally designed. Numerical results show that the principal formula is accurate in that, for rate R=$log_2N{\geq}6$, it predicts signal-to-noise ratios within 1% of the true values for a wide range of $\mu$, and $\rho$. The new findings herein include the fact that, for heavy variance mismatch of ${\rho}>3/2$, the signal-to-noise ratio increases at the rate of $9/\rho$ dB/bit, which is slower than the usual 6 dB/bit, and the fact that an optimal uniform quantizer, though optimally designed, is slightly more than critically mismatched to the source. It is also found that signal-to-noise ratio loss due to $\mu$ is moderate. The derived formulas can be useful in quantization of speech or music signals, which are modeled well as Laplacian sources and have changing short-term variances.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.7
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• pp.4842-4848
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• 2015

This paper presents a comparison of communication performance between the reconfigurable beam-steering antenna and the omni-directional (loop) antenna during standstill and walking motion. Both omni-directional and reconfigurable antennas were manufactured on the same fabric (${\varepsilon}_r=1.35$, $tqn{\delta}=0.02$) substrate and operated around 5 GHz band. The reconfigurable antenna was designed to steer the beam directions. To implement the beam-steering capability, the antenna used two PIN diodes. The measured peak gains were 5.9-6.6 dBi and the overall half power beam width (HPBW) was $102^{\circ}$. In order to compare the communication efficiency, both the bit error rate (BER) and the signal-to-noise ratio (SNR) were measured using a GNU Radio Companion software tool and user software radio peripheral (USRP) devices. The measurement were performed when both antennas were standstill and walking motion in an antenna chamber as well as in a smart home environment. From these results, the performances of the reconfigurable beam steering antenna outperformed that of the loop antenna. In addition, in terms of communication efficiencies, in an antenna chamber was better than in a smart home environment. In terms of movement of antennas, standstill state has better results than walking motion state.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.7
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• pp.657-663
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• 2009

A fully integrated single ended IR-UWB receiver is implemented using 0.18 ${\mu}m$ CMOS technology. The UWB receiver adopts the non-coherent architecture, which simplifies the RF architecture and reduces power consumption. The receiver consists of single-ended 2-stage LNAs, S2D, envelope detector, VGA, and comparator. The measured results show that sensitivity is -80.8 dBm at 1 Mbps and BER of $10^{-3}$. The receiver uses no external balun and the chip size is only $1.8{\times}0.9$ mm. The consumed current is very low with 13 mA at 1.8 V supply and the energy per bit performance is 23.4 nJ/bit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.905-912
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• 2007

This paper proposes an efficient estimation and compensation scheme of IQ imbalance for OFDM-based WLAN systems in the presence of symbol timing error. Since the conventional scheme assumes perfect time synchronization, the criterion of the scheme used to derive the estimation of IQ imbalance is inadequate in the presence of the symbol timing error and the system performance is seriously degraded. New criterion and compensation scheme considering the effect of symbol timing error are proposed. With the proposed scheme, the IQ imbalance can be almost perfectly eliminated in the presence of symbol timing error. The bit error rate performance of the proposed scheme is evaluated by the simulation. In case of 54 Mbps transmission mode in IEEE 802.11a system, the proposed scheme achieves a SNR gain of 4.3dB at $BER=2{\cdot}10^{-3}$. The proposed compensation algorithm of IQ imbalance is implemented using Verilog HDL and verified. The proposed IQ imbalance compensator is composed of 74K logic gates and 6K bits memory from the synthesis result using 0.18um CMOS technology.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.5
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• pp.155-161
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• 2009

This paper proposes a high capacity data hiding method using modulus function of pixel-value differencing (PVD) and least significant bit (LSB) replacement method. Many novel data hiding methods based on LSB and PVD methods were presented to enlarge hiding capacity and provide an imperceptible quality. A small difference value for two consecutive pixels is belonged to a smooth area and a large difference one is located on an edge area. In our proposed method, the secret data are hidden on the smooth area by the LSB substitution method and PVD method on the edge area. From the experimental results, the proposed method sustains a higher capacity and still a good quality compared with other LSB and modified PVD methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8C
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• pp.591-597
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• 2008

In this paper, we present a improved rate distortion optimization (RDO) for H.264 intra coding. By using new mode decision criteria pass for $I4{\times}4$ in company with the original RDO, the proposed method can achieve the better coding efficiency comparing with the original RDO. Our experimental results show that the proposed algorithm can archive about $0.64{\sim}1.6578%$ bit rate decrease at the same PSNR and $0.049{\sim}0.101dB$ PSNR increase at the same bit rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.9-17
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• 2004

Adapt ive and fixed step size PC (power control) schemes for accommodating voice, video, and data are evaluated according to the different PC command rates and their effects on integrated Voice/Video/Data are investigated. The required minimum power levels are derived as PC thresholds and the effects of PC errors on channel quality and radio 1 ink capacity are investigated. The services with high bit rates and low bit error rates can cause a significant effect on the radio link qualifies of the other types of traffic. The results show that the adapt ive step size PC scheme for voice/video/data services can achieve more capacity and cause less interference to the radio channels because less minimum PIL(Power Increment Level) is required for the specified radio link outage probability.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1073-1081
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• 2005

This paper describes a 3.3 V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method. Most of Dfh converters with hiか speed current drive are an architecture choosing current switch cell, column, row decoding method but this decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. The designed D/A converter with an active chip area of $0.953\;mm^2$ is fabricated by using a 0.35um process. The simulation data shows that the rise/fall time, settling time, and INL/DNL are 1.92/2.1 ns, 12.71 ns, and a less than ${\pm}2.3/{\pm}58$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3 V is about 224 mW.