• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.613-618
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• 2015

This paper proposed a low power CMOS Flash-SAR A/D converter which consists of a Flash A/D converter for 2 most significant bits and a SAR A/D converter with capacitor D/A converter for 8 least significant bits. Employment of a Flash A/D converter allows the proposed circuit to enhance the conversion speed. The SAR A/D converter with capacitor D/A converter provides a low power dissipation. The proposed A/D converter consumes $136{\mu}W$ with a power supply of 1V under a $0.18{\mu}m$ CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).

• The Journal of the Acoustical Society of Korea
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• v.21 no.5
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• pp.462-470
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• 2002

Wideband speech, characterized by a bandwidth of 50∼7000 ㎐, sounds more natural and intelligible, and is less tiring to listen to when compared to narrowband speech characterized by a bandwidth of 300∼3400 ㎐. Wideband speech coders, however, have not been as successful as the narrowband speech coders because of their higher bit rate. In this paper, we propose a new wideband speech coder which combines the European standard of a narrowband speech coder, i.e., GSM-EFR, and a transform coder using the discrete wavelet transform. The proposed wideband speech coder operates as follows input speech is first split into two subbands with equal bandwidth and the two subband signals are coded and decoded by each subband coder. A GSM-EFR is adopted as a lower subband coder and a subband coder with wavelet transformed speech is designed for a upper subband coder. The total bit rate of the proposed coder is 18.9kbps (12.2 kbps for lower band coder and 6.7 kbps for upper band coder), and informal listening test results have shown that the proposed coder has comparable speech quality to that of G.722 with 56 kbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.9
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• pp.728-737
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• 2012

An analytical method for identifying terrestrial broadcasting coverages is proposed for a terrestrial broadcasting transmission system adopting a hierarchical modulation technique. Bit Error Rates(BERs) are derived for hierarchically modulated non-uniform QAM constellations based on the Q-function analysis in AWGN environments. The derived BERs depend on the hierarchical modulation factor ${\alpha}$(HMF) and could be mapped to the broadcasting coverages according to the link budget analysis based on the log-distance path loss model. Finally the broadcasting coverage ratios for high priority(HP) streams and low priority(LP) streams are calculated and presented for the determination of the HMF.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5C
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• pp.536-541
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• 2007

In video coding standard H.264/AVC, motion estimation using multiple reference pictures improves compression efficiency but the efficiency depends upon image content not the number of reference pictures. So, the motion estimation includes a large amount of computation of no worth according to image. This paper proposes fast motion estimation algorithm that removes worthless computation in the motion estimation using multiple reference pictures. The proposed algorithm classifies a block into valid and invalid blocks for the multiple reference pictures and removes the workless computation by applying a single reference picture to the invalid block. To estimate the proposed algorithm's performance, image quality, bit rate, and motion estimation time are compared with ones of the conventional algorithm in the reference software JM 9.5. The simulation results show that the proposed algorithm can considerably save about 38.67% the averaged motion estimation time while keeping the image quality and the bit rate, whose are average values are -0.02dB and -0.77% respectively, as good as the conventional algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.303-309
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• 2013

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.750-758
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• 2013

In this paper, we introduce the low-density parity-check (LDPC) coded orthogonal frequency division multiplexing (OFDM) subframe reordering scheme for achieving equal combined power allocation in type I hybrid automatic repeat request (H-ARQ) systems and analyze the performance improvement by using the channel capacity. Also, it is confirmed that the layered decoding for subframe reordering scheme in H-ARQ systems gives faster convergence speed. It is verified from numerical analysis that a subframe reordering pattern having larger channel capacity shows better bit error rate (BER) performance. Therefore the subframe reordering pattern achieving equal combined power allocation for each subframe maximizes the channel capacity and outperforms other subframe reordering patterns. Also, it is shown that the subframe reordering scheme for achieving equal combined power allocation gives better performance than the conventional Chase combining scheme without increasing the decoding complexity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.9
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• pp.2153-2160
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• 2015

An analysis of hardware design conditions of moving object detection (MOD) algorithm is described, which is based on effective Gaussian mixture learning (EGML). A simulation model of EGML algorithm is implemented using OpenCV, and the effects of some parameter values on background learning time and MOD sensitivity are analyzed for various images. In addition, optimal design conditions for hardware implementation of EGML-based MOD algorithm are extracted from fixed-point simulations for various bit-widths of parameters. The proposed fixed-point model of the EGML-based MOD uses only half of the bit-width at the expense of the loss of MOD performance within 0.5% when compared with floating-point MOD results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1654-1665
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• 2008

This paper presents bit splitting methods to apply multilevel modulation to iterative codes such as turbo code, low density parity check code and turbo product code. Log-likelihood ratio method splits multilevel symbols to soft decision symbols using the received in-phase and quadrature component based on Gaussian approximation. However it is too complicate to calculate and to implement hardware due to exponential and logarithm calculation. Therefore this paper presents Euclidean, MAX, sector and center focusing method to reduce the high complexity of LLR method. Also, this paper proposes optimal soft symbol split method for three kind of iterative codes. Futhermore, 16-APSK modulator method with double ring structure for applying DVB-S2 system and 16-QAM modulator method with lattice structure for T-DMB system are also analyzed.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.2
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• pp.27-32
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• 2021

This paper proposes an energy-efficient cache and memory management scheme for next-generation IoT devices. The proposed scheme adopts a low-power phase-change memory (PCM) as the main memory of IoT devices, aims at minimizing the write traffic to PCM, which is vulnerable to write operations. Specifically, when a cache block of the last-level cache memory is flushed to main memory, the cache block that causes less writes to PCM is preferentially replaced by tracking the modifications of each cache line that constitutes the cache block. In addition, by considering the reference bit of the cache block and the dirty bit of the cache lines, our scheme reduces the energy consumption without degrading the memory system performances. Through simulations using SPEC benchmarks, it is shown that the proposed scheme reduces the write traffic to PCM by 34.6% on average and the power consumption by 28.9%, without memory performance degradations.