• JOURNAL OF ELECTRICAL WORLD
• /
• no.11 s.107
• /
• pp.84-89
• /
• 1985

최근 산업분야에 있어서의 자동화의 니이즈는 다양화되어 그 양상은 극에 달하고 가장 적당한 시스템을 구축하는 기술이 보다 중요시하게 되었다. 특히 분산과 집중을 어떻게 조화시키느냐가 초점이 되어있다. 1975년 IEC에서는 공업용데이터웨이 P-roway의 규격을 제정하도록 결정했다. 이 결정으로 1기업의 공장내$\cdot$동일빌딩내$\cdot$창고등 한정된 지역에 있어서의 생산관리정보 등의 통신용의 네트워크로서 LAN이 실용화하게 되고 1980년 IEEE 802위원회에서 표준화 활동이 개시됨으로서 현재 기술적으로는 거의 대부분의 표준은 완성하기에 이르렀다. 한편 산업분야에 있어서의 FA화는 현저한 진전을 보이고 있으며 보다 효율적인 시스템을 구축하는데 있어서 네트워크$\cdot$시스템은 필수적인 요소가 되고 있다. 여기서는 FA에 있어서 네트워크$\cdot$시스템을 계획$\cdot$구축해 가는데 있어 요점초점이 되는 과제에 대하여 해설 그 사례에 대해서 기술하기로 한다.

• Journal of Communications and Networks
• /
• v.15 no.2
• /
• pp.179-190
• /
• 2013

Given the bandwidth assignment for dedicated short range communications for use in vehicular ad-hoc network (VANET) and the expected introduction of equipment in the next few years, we elaborate on how VANET can support infotainment services. We define an architectural model for the integration of VANETs and cellular networks, according to a push mode paradigm where VANETs are used primarily to disseminate service announcements and general interest messages. Cooperation with cellular network is addressed by comparing architecture alternatives. A set of information dissemination protocols for VANETs is compared via simulations on a real urban map. Some results from a lab testbed based on IEEE 802.11p boards are presented along with an application developed for Android operating system to demonstrate the concept of the paper.

• Journal of Communications and Networks
• /
• v.15 no.2
• /
• pp.132-141
• /
• 2013

In this paper, we present diversity coded orthogonal frequency division multiplexing (DC-OFDM), an approach to maximize the probability of successful reception and increase the reliability of OFDM-based systems through diversity coding. We focus on the application of DC-OFDM to vehicular networks based on IEEE 802.11p technology and analyze the performance improvement using this new technology. It is shown that DC-OFDM significantly improves the performance of vehicular ad hoc networks in terms of throughput and the expected number of correctly received symbols.

• Journal of Auto-vehicle Safety Association
• /
• v.12 no.4
• /
• pp.48-53
• /
• 2020

This paper describes in work which is currently underway to the minimum safety performance requirements and test methods of V2V based on IEEE 802.11p in vehicle level like below. - The ranges and positions at static and driving condition of vehicle for BSM (Basic safety message) - Various road conditions such as straight road, crossroad, slope-way Based on this study, We will define the minimum safety performance requirements and test methods of V2V in vehicle considering various road conditions.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.10 no.2
• /
• pp.608-627
• /
• 2016

Wireless mesh networks (WMNs) based on IEEE 802.11s have emerged as one of the prominent technologies in multi-hop communications. However, the deployment of WMNs suffers from serious interference problem which severely limits the system capacity. Using multiple radios for each mesh router over multiple channels, the interference can be reduced and improve system capacity. Nevertheless, interference cannot be completely eliminated due to the limited number of available channels. An effective approach to mitigate interference is to apply dynamic channel switching (DCS) in WMNs. Conventional DCS schemes trigger channel switching if interference is detected or exceeds a predefined threshold which might cause unnecessary channel switching and long protocol overheads. In this paper, a P-learning based dynamic switching algorithm known as learning automaton (LA)-based DCS algorithm is proposed. Initially, an optimal channel for communicating node pairs is determined through the learning process. Then, a novel switching metric is introduced in our LA-based DCS algorithm to avoid unnecessary initialization of channel switching. Hence, the proposed LA-based DCS algorithm enables each pair of communicating mesh nodes to communicate over the least loaded channels and consequently improve network performance.

• ETRI Journal
• /
• v.42 no.5
• /
• pp.773-780
• /
• 2020

A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

• Journal of Internet Computing and Services
• /
• v.14 no.1
• /
• pp.15-22
• /
• 2013

WAVE(Wireless Access for Vehicular Environment) is new concepts and Vehicles communications technology using for ITS(Intelligent Transportation Systems) service by IEEE standard 802.11p. Also it increases the efficiency and safety of the traffic on the road. However, the efficiency of Scrambler bit computational algorithms of OFDM modulation in WAVE systems will fall as it is not able to process in parallel in terms of hardware and software. This paper proposes an algorithm to configure 64-bits matrix table in scambler bit computation as well as an algorithm to compute 64-bits matrix table and input data in parallel. The proposed algorithm on this thesis is executed using 64-bits matrix table. In the result, the processing speed for 1 and 1000 times is improved about 40.08% ~ 40.27% and processing rate per sec is performed more than 468.35 compared to bit operation scramble. And processing speed for 1 and 1000 times is improved about 7.53% ~ 7.84% and processing rate per sec is performed more than 91.44 compared to 32-bits operation scramble. Therefore, if the 64 bit-CPU is used for 64-bits executable scramble algorithm, it is improved more than 40% compare to 32-bits scrambler.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.4
• /
• pp.53-63
• /
• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.6A
• /
• pp.634-639
• /
• 2006

In this paper an MMIC 2-stage power amplifier is designed and fabricated for 5GHz wireless LAN applications using $0.5{\mu}m$ gate length PHEMT transistors. The PHEMT gate width is optimized in order to meet the linearity and efficiency of the MMIC power amplifier. The $0.5{\mu}m\times600{\mu}m$ PHEMT for the drive stage and $0.5{\mu}m\times3000{\mu}m$ PHEMT for the amplification stage are the optimized sizes to achieve more than 25dBc of third order IMD at the power level of 3dB back-off from the input P1dB and more than 22dBm output power under a supply voltage of 3.3V. The two-stage MMIC power amplifier is designed to be used for the both of HIPERLAN/2 and IEEE 802.11a because of its broadband characteristics. The fabricated PHEMT MMIC power amplifier exhibits a 20.1dB linear power gain, a maximum 22dBm output power, a 24% power added efficiency under 3.3V supply voltage. The input and output on-chip matching circuits are included on a chip of $1400\times1200{\mu}m^2$.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.8 s.350
• /
• pp.91-96
• /
• 2006

High efficiency switching mode circuits such as class I amplifiers have been well known in the MHz frequency range. The class E amplifier is a type of switching mode amplifier offering very high efficiency approaching 100%. In this paper, the class E amplifier has been designed by using the harmonic balance method of circuit simulator. The designed amplifier is realized by using pHEMT and microstrip line, shows 66% power added efficiency (PAE) at 2.4GHz with 17.6dBm output power. With -3dBm input power of wireless LAN, measured output spec01m can meet the required IEEE 802.11g standard spectrum mask. That means the required amplifier back off of 9dB from $P_{ldB}$ to satisfy the required wireless LAN spectrum mask.