• 제목/요약/키워드: 8-bit single chip controller

검색결과 5건 처리시간 0.032초

바이러스 감염 판별용 혈액 검사기 개발 (The development of Inspection Machine for a blood virus infection)

  • 전재민;서규태;이보희;이인구;민승기;김학준
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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    • pp.465-467
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    • 2004
  • This paper deals with the design and analysis of automatic virus infection machine, which can be used in blood testing at veterinary hospital. It consists of the mechanical positioning parts and electrical control parts. Two of driving motor and ball screws are used to move the liquid container into the test position and mix the blood on litmus paper. In addition, a thermal controller is installed to keep the container temperature on constant level. The user interface using with a LCD and some keys are supplied with a 8-bit single chip controller. All of the designs issue related with the mechanism and controllers are discussed in detail. Finally the proposed machine is tested in real experiment with the formal processing to judge the virus infection, and also the usefulness of designed algorithm is verified through the experiments.

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FPGA를 이용한 CAN 통신 IP 설계 및 구현 (Design and Implementation of CAN IP using FPGA)

  • 손예슬;박정근;강태삼
    • 제어로봇시스템학회논문지
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    • 제22권8호
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    • pp.671-677
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    • 2016
  • A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

신경 제어기에 의한 Photovoltaic System의 MPPT구현에 관한 연구 (A study on the MPPT(Maximum Power Point Tracking) for Photovoltaic System using Neural Controller)

  • 차인수;최장균;유권종
    • 태양에너지
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    • 제18권1호
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    • pp.27-34
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    • 1998
  • 태양광 발전 시스템의 운용에 있어서 부하의 변동, 일사량, 주변온도등에 의한 최대전력점의 추종은 매우 어려운 기술을 요구한다. 본 연구에서는 이러한 최대전력점의 추종에 있어 빠른 수렴 특성을 얻기 위한 알고리즘으로써 신경 제어기법을 이용하여서 기존의 제어 방식에 의한 동특성과 비교하여 적절한 제어기법 및 시스템동작의 우수한 특성을 얻게 되었다. 즉 최대전력점의 추종 및 안정한 전원의 공급을 갖게되었다.

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퍼지제어기를 이용한 에어콘 구동용 태양광 발전시스템의 최대전력점추종 방법 (The Maximum Power Point Tracking of Photovoltaic System for Air Conditioning System using Fuzzy Controller.)

  • 강병복;차인수;유권종;정명웅;송진수
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1996년도 하계학술대회 논문집 A
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    • pp.600-602
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    • 1996
  • The purpose of this paper is to develop a new maximum power point tracking(MPPT) using fuzzy set theory for air conditioning system. Fuzzy algorithm based on linguistic rules describing the operator's control strategy is applied to control step-up chopper for MPPT. Fuzzy algorithm is applied to control boost MPPT converter by temperature compensation effect with 8 bit single chip 8051 microcontroller. In this paper, temperature compensation(Becom Transducer : pf-T type) range is $-40^{\circ}C{\sim}+100^{\circ}C$.

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내장형 32비트 RISC 콘트롤러의 VLSI 구현 (A VLSI implementation of 32-bit RISC embedded controller)

  • 이문기;최병윤;이승호
    • 전자공학회논문지A
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    • 제31A권10호
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    • pp.141-151
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    • 1994
  • this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.

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