• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.465-467
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• 2004

This paper deals with the design and analysis of automatic virus infection machine, which can be used in blood testing at veterinary hospital. It consists of the mechanical positioning parts and electrical control parts. Two of driving motor and ball screws are used to move the liquid container into the test position and mix the blood on litmus paper. In addition, a thermal controller is installed to keep the container temperature on constant level. The user interface using with a LCD and some keys are supplied with a 8-bit single chip controller. All of the designs issue related with the mechanism and controllers are discussed in detail. Finally the proposed machine is tested in real experiment with the formal processing to judge the virus infection, and also the usefulness of designed algorithm is verified through the experiments.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• Solar Energy
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• v.18 no.1
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• pp.27-34
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• 1998

A maximum power point tracking(MPPT) converter, to enhance the converter efficiency is evaluated within the laboratory. The converter is controlled to track the maximum power point of the input photovoltaic(PV) source by varying the input and output parameter-conditions of irradiation, temperature, etc. The purpose of this paper is to develop a new maximum power point tracking(MPPT) using neural controller. Neural controller are applied to control of MPPT by boosting converter duty ratios compensation effect with 8 bit single chip 8051 microcontroller.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.600-602
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• 1996

The purpose of this paper is to develop a new maximum power point tracking(MPPT) using fuzzy set theory for air conditioning system. Fuzzy algorithm based on linguistic rules describing the operator's control strategy is applied to control step-up chopper for MPPT. Fuzzy algorithm is applied to control boost MPPT converter by temperature compensation effect with 8 bit single chip 8051 microcontroller. In this paper, temperature compensation(Becom Transducer : pf-T type) range is $-40^{\circ}C{\sim}+100^{\circ}C$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.141-151
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• 1994

this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.