• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.1
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• pp.29-38
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• 2012

Due to the rapid development of network environment and wireless communication technology, the distribution of digital video has made easily and the importance of the protection for digital video has been increased. This paper proposes the digital video encryption system based on multiple chaos maps for MPEG-2 video encoding process. The proposed method generates secret hash key of having 128-bit characteristics from hash chain using Tent map as a basic block and generates $8{\times}8$ lattice cipher by applying this hash key to Logistic map and Henon map. The method can reduce the encryption overhead by doing selective XOR operations between $8{\times}8$ lattice cipher and some coefficient of low frequency in DCT block and it provides simple and randomness characteristic because it uses the architecture of combining chaos maps. Experimental results show that PSNR of the proposed method is less than or equal to 12 dB with respect to encrypted video, the time change ratio, compression ratio of the proposed method are 2%, 0.4%, respectively so that it provides good performance in visual security and can be applied in real time.

• The Journal of the Acoustical Society of Korea
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• v.20 no.6
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• pp.34-39
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• 2001

An adaptive multi-rate (AMR) speech coder was adopted as a standard of W-CDMA by 3GPP and ETSI. The AMR coder is based on the CELP algorithm operating at rates ranging from 12.2 kbps down to 4.75 kbps, and it is a source controlled codec according to the channel error conditions and the traffic loading. In this paper, we implement the DSP S/W of the AMR coder using OakDSPCore. The implementation is based on the CSD17C00A chip developed by C&S Technology, and it is tested using test vectors, for the AMR speech codec, provided by ETSI for the bit exact implementation. The DSP B/W requires 20.6 MIPS for the encoder and 2.7 MIPS for the decoder. Memories required by the Am coder were 21.97 kwords, 6.64 kwords and 15.1 kwords for code, data sections and data ROM, respectively. Also, actual sound input/output test using microphone and speaker demonstrates its proper real-time operation without distortions or delays.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.1
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• pp.47-57
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• 2003

In this paper, we firstly evaluate the resistance of the reduced 5-round version of the block cipher CIKS-1 against linear cryptanalysis(LC) and show that we can attack full-round CIKS-1 with \ulcorner56-bit key through the canonical extension of our attack. A feature of the CIKS-1 is the use of both Data-Dependent permutations(DDP) and internal key scheduling which consist in data dependent transformation of the round subkeys. Taking into accout the structure of CIKS-1 we investigate linear approximation. That is, we consider 16 linear approximations with p=3/4 for 16 parallel modulo $2^2$ additions to construct one-round linear approximation and derive one-round linear approximation with the probability P=1/2+$2^{-17}$ by Piling-up lemma. Then we present 3-round linear approximation with 1/2+$2^{-17}$ using this one-round approximation and attack the reduced 5-round CIKS-1 with 64-bit block by LC. In conclusion we present that our attack requires $2^{38}$chosen plaintexts with a probability of success of 99.9% and about $2^{67-7}$encryption times to recover the last round key.(But, for the full-round CIKS-1, our attack requires about $2^{166}$encryption times)

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.8-14
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• 2012

Improving the speed of image processing is in great demand according to spread of high quality visual media or massive image applications such as 3D TV or movies, AR(Augmented reality). SIMD computer attached to a host computer can accelerate various image processing and massive data operations. MAMS is a multi-access memory system which is, along with multiple processing elements(PEs), adequate for establishing a high performance pipelined SIMD machine. MAMS supports simultaneous access to pq data elements within a horizontal, a vertical, or a block subarray with a constant interval in an arbitrary position in an $M{\times}N$ array of data elements, where the number of memory modules(MMs), m, is a prime number greater than pq. MAMS-PP4 is the first realization of the MAMS architecture, which consists of four PEs in a single chip and five MMs. This paper presents implementation of image processing algorithms and performance analysis for MAMS-PP16 which consists of 16 PEs with 17 MMs in an extension or the prior work, MAMS-PP4. The newly designed MAMS-PP16 has a 64 bit instruction format and application specific instruction set. The author develops a simulator of the MAMS-PP16 system, which implemented algorithms can be executed on. Performance analysis has done with this simulator executing implemented algorithms of processing images. The result of performance analysis verifies consistent response of MAMS-PP16 through the pyramid operation in image processing algorithms comparing with a Pentium-based serial processor. Executing the pyramid operation in MAMS-PP16 results in consistent response of processing time while randomly response time in a serial processor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.

• Journal of Soil and Groundwater Environment
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• v.14 no.1
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• pp.29-35
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• 2009

In this study, the effect of pH and temperature on the adsorption behavior of acid mine drainage (AMD) on coal mine drainage sludge (CMDS) has been investigated during the treatment of coal mine drainage (CMD) by electrical purification method. The pH$_{zero\;point\;charge}$ (pH$_{zpc}$) of CMDS was 5. The removal ratio of copper, zinc, cadmium, iron were increased according to the increase of pH value. The adsorption amount of copper showed 0.64 mg g$^{-1}$ sludge. It was independent of pH value. The adsorption amount of the other metals showed l.l times when pH was 3. The adsorption amount of chromium was a little bit increased at the pH value higher than 7 due to a small amount of the chromium was eluted as $Cr(OH)_6^{3-}$. The amount of metals' absorption were decreased according to temperature was increase at pH value was 3. The selectivity order was Cd>Fe > Zn > Cu. The amount of absorption showed q$_{max}$ Cu 2.747 mg g$^{-1}$ andZn 2.525 mg g$^{-1}$ when pH value higher than 5. It was independent of temperature.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.48-58
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• 2006

This paper presents 8x8 two dimensional DCT/IDCT processor of adder-based distributed arithmetic architecture without applying ROM units in conventional memories. To reduce hardware cost in the coefficient matrix of DCT and IDCT, an odd part of the coefficient matrix was shared. The proposed architecture uses only 29 adders to compute coefficient operation in the 2-D DCT/IDCT processor, while 1-D DCT processor consists of 18 adders to compute coefficient operation. This architecture reduced 48.6% more than the number of adders in 8x8 1-D DCT NEDA architecture. Also, this paper proposed a form of new transpose network which is different from the conventional transpose memory block. The proposed transpose network block uses 64 registers with reduction of 18% more than the number of transistors in conventional memory architecture. Also, to improve throughput, eight input data receive eight pixels in every clock cycle and accordingly eight pixels are produced at the outputs.

• Journal of the Korea Society of Computer and Information
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• v.17 no.1
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• pp.1-10
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• 2012

Improving operating frequency of processors is no longer today's issues; a multiprocessor technique which integrates many processors has received increasing attention. Currently, high-performance processors that integrate 64 or 128 cores are developing for large data processing over 2, 4, or 8 processor cores. This paper proposes an optimal many-core processor for synthesizing guitar sounds. Unlike the previous research in which a processing element (PE) was assigned to support one of guitar strings, this paper evaluates the impacts of mapping different numbers of PEs to one guitar string in terms of performance and both area and energy efficiencies using architectural and workload simulations. Experimental results show that the maximum area energy efficiencies were achieved at PEs=24 and 96, respectively, for synthesizing guitar sounds with sampling rate of 44.1kHz and 16-bit quantization. The synthesized sounds were very similar to original guitar sounds in their spectra. In addition, the proposed many-core processor was 1,235 and 22 times better than TI TMS320C6416 in area and energy efficiencies, respectively.

• Journal of The Korean Association For Science Education
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• v.34 no.7
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• pp.647-655
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• 2014

The purpose of this study is to acquire teaching insights for improving scientific literacy by analyzing the effects of scientific communication skills, science process skills, and logical thinking skills of elementary school students on academic achievement level. The participants are 64, sixth grade elementary school students. Survey materials include the results of Scientific Communication Skill Test (SCST), Test of Science Process Skills (TSPS), Group Assessment of Logical Thinking (GALT), multiple choice test & short answer test, descriptive answer test on science, and academic achievement level test on all subjects. Based on these data, the study analyzed the relationships of science process skills, logical thinking skills, and scientific communication skills, and each category's effect on academic achievement level. Furthermore, under the assumption that scientific communication skills are affected by science process skills and logical thinking skills and directly influence the academic level, the research discovered three types of correlations as a structural model. The results show that there are considerable correlations in scientific communication skills, science process skills, and logical thinking skills. Also, these three abilities have meaningful correlations with learner's writing and descriptive question level on science curriculum and overall academic achievement level; the level of correlation differ a bit by subcategory factors. In conclusion, setting the model, science process skills and logical thinking skills influence scientific communication skill, and the skill directly influences the learner's academic level. Further analysis of the results show that scientific communication skill influences the academic achievement level of all subjects the most.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.212-224
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• 1998

There are two major factors of degrading the performance in the forward link of DS/CDMA systems. One is the multiple access interference (MAI) caused by using the same frequency bands simultaneously and the other is the multipath lading due to multipath propagation. PN codes which have minimum cross correlation properties among spread spectrum codes are necessary to reduce the MAI. In the conventional IS-95A system, the PN sequence has the period of $2^{15}$ and is of the length of 64 chips for spreading each data. In this case, since the length of PN code per bit is very short compared to the period of the PN code, the performance of the conventional system is not satisfied in view of suppressing the multipath interference. However, the correlation property of the PN codes at the demodulation can be improved by increasing the interval of Integration at the demodulation. This paper proposes a demodulation method to reduce the cross correlation among PN codes. The performance of the proposed demodulation method is investigated through computer simulations. We used multipath Ray lading channel and AWGN channel in the simulation. Our simulation results show the improved performance of $0.25{\sim}0.5dB$ SNR in a given BER compared to the conventional demodulation scheme.