• 제목/요약/키워드: 5.8 GHz

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Design of the Wideband Notched Compact UWB Antenna (넓은 대역폭이 소거된 소형 UWB 안테나 설계)

  • Kim, Cheol-Bok;Lim, Jung-Sup;Lee, Ho-Sang;Jang, Jae-Sam;Jung, Young-Ho;Jo, Dong-Ki;Lee, Mun-Soo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.9
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    • pp.54-62
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    • 2007
  • In this paper, a novel wideband notched compact UWB antenna is designed to satisfy the licensed UWB frequency bandwidth($3.1{\sim}4.8$ GHz, $7.1{\sim}10.2$ GHz) by symmetrically arranging two adjacent sectorial loop antennas. The wideband($4.8{\sim}7.1$ GHz) notch can be obtained by inserting the inverted-L shaped slits on the patch. The designed UWB antenna has return loss lower than -10dB at 3.1 GHz and over, group delay value lower than 1 ns and the linear phase property. The optimized UWB antenna inserted the inverted-L shaped slits has return loss great than -10dB, 5 ns of group delay, nonlinear phase and decreased gain properties over the frequency band, 4.8 GHz to 7.1 GHz.

2-6 GHz Digital Phase Shifter Module (2-6 GHz 디지털 위상변위기 모듈)

  • Jeong, Myeong-Deuk;So, Jun-Ho;U, Byeong-Il;Im, Jung-Su;Lee, Sang-Won;Park, Dong-Cheol
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.39 no.3
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    • pp.158-164
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    • 2002
  • 2-6 GHz digital phase shifter module has been designed and fabricated. For the broadband operation and performance, MMIC phase shifter chip for phase shifter module was designed and fabricated by using the reflection-type circuits with Lange coupler. The fabricated phase shifter module shows 6.1$^{\circ}$RMS phase error, 13.5 dB maximum insertion loss, and 8 dB and 10 dB input and output return losses, respectively. Computer controlled measurement systems are realized in order to get the measured data of 32 phase states. The RMS insertion phase error and the average insertion loss deviation among 8${\times}$8 modules for the phased-array system are less than ${\pm}$0.5$^{\circ}$and ${\pm}$0.5 dB, respectively. The size of fabricated phase shifter module is 45 ${\times}$ 22.5 ${\times}$60㎣.

위성통신용 수신기의 설계

  • 정우영;백정기;최부귀
    • Journal of Korea Society of Industrial Information Systems
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    • v.1 no.1
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    • pp.119-233
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    • 1996
  • 본 논문에서는 게이트의 길이가 0.25$\mu\textrm{m}$dlsGaAs HEMT(High Electron Mobility Transistor)를 이용하여 11.7GHz-12.2GHz 대역 위성통신용 수신기를 설계하였다. 설계된 수신기의 전체이득은 38dB 이상, 잡음지수 1.8dB 이하, 입출력단의 반사손실은 -10dB 이하를 보였다. 수신기는 저잡음증폭기(LNA), 중간주파수증폭기(IFA) , 믹서(Mixer), 국부발진기(LO) 로 구성되어 있으며 LO 주파수와 IF 주파수는 각각 10.75GHz 와 0.95GHz-1.45GHz이고 칩의 크기는 1.7mm $\times$2.5mm이다.

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위성통신용 수신기의 설계

  • 정우영;백정기;최부귀
    • Proceedings of the Korea Society for Industrial Systems Conference
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    • 1996.10a
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    • pp.184-195
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    • 1996
  • 본 논문에서는 게이트의 길이가 0.25um인 GaAs HEMT를 이용하여 11.7GHz -12.2GHz 대역 위성통신용 수신기를 설계하였다. 설계된 수신기의 전체이득은 38dB 이상, 잡음지수 1.8dB 이하, 입출력단의 반사손실은 -10dB 이하를 보였다. 수신기는 저잡음증폭기(LNA), 중간주파수증폭기(IFA) , 믹서, 국부발진기(LO) 로 구성되어 있으며 LO 주파수와 IF 주파수는 각각 10.75GHz 와 0.95GHz-1.45GHz이고 칩의 크기는 1.7mm $\times$2.5mm이다.

Design of a High-Resolution DCO Using a DAC (DAC를 이용한 고해상도 DCO 설계)

  • Seo, Hee-Teak;Park, Joon-Ho;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.7
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    • pp.1543-1551
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    • 2011
  • Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a $0.13{\mu}m$ CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is $1.3mm{\times}1.3mm$ including pads.

The study of the packaging for Ti:LiN$bO_3$optical modulator device and its electrical and optical characteristics (Ti:LiN$bO_3$ 광변조기 소자의 패키징 및 전기.광학적 특성)

  • 윤형도;김성구;이한영;윤대원
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.6
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    • pp.72-78
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    • 1998
  • An optical modulator Ti:LiNbO$_3$optical waveguide and CPW electrode structure were fabricated. The optical modulator was packaged using components such as ferrules, dirmy LN block and glass, vibration and shock absorbption pad, and alumina feeder through processings of pigtailing. Au wire bonding, epoxing, SMA connecting, sealing. The electrical and optical characteristics were measured after packaging. The electrical properties of S$_{21}$ and S$_{11}$ were obtained as 9.8 GHz at -3 dB and -8.9dB at 14.4GHz, respectively. Optical waveguide prepared met requirements for a single mode at a 1550nm wavelength range. Insertion loss was 4.3dB at room temperature after packaging, and was varied 4.3~6.4dB at various temperatures, 5~45$^{\circ}C$. E-O bandwidth measurement showed 3dB optical response at 7.8GHz, which means that it is applicable for 10Gbps optical communicationon

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Design of a V Band Power Amplifier Using 65 nm CMOS Technology (65 nm CMOS 공정을 이용한 V 주파수대 전력증폭기 설계)

  • Lee, Sungah;Cui, Chenglin;Kim, Seong-Kyun;Kim, Byung-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.4
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    • pp.403-409
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    • 2013
  • In this work, a CMOS two stage differential power amplifier which includes Marchand balun, transformer and injection-locked buffer is presented. The power amplifier is targeted for 70 GHz frequency band and fabricated using 65 nm technology. The measurement results show 8.5 dB maximum voltage gain at 71.3 GHz and 7.3 GHz 3 dB bandwidth. The measured maximum output power is 8.2 dBm, input $P_{1dB}$ is -2.8 dBm, output $P_{1dB}$ is 4.6 dBm and maximum power added efficiency is 4.9 %. The power amplifier consumes 102 mW DC power from 1.2 V supply voltage.

Design and Fabrication of Quadruple Band Antenna with DGS (DGS를 적용한 4중대역 안테나의 설계 및 제작)

  • Kim, Min-Jae;Choi, Tea-Il;Choi, Young-Kyu;Yoon, Joong-Han
    • The Journal of the Korea institute of electronic communication sciences
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    • v.15 no.1
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    • pp.31-38
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    • 2020
  • In this paper, we propose a quadruple band antenna for GPS/WLAN/WiMAX application. The proposed antenna has quadruple band characteristics by considering the interconnection of four strip lines and DGS on the ground place. The total substrate size is 20.0 mm (W1) ⨯27.0 mm (L1), thickness (h) 1.0 mm, and the dielectric constant is 4.4, which is made of 20.0 mm (W2)⨯ 27.0 mm (L8 + L6+ L10) antenna size on the FR-4 substrate. From the fabrication and measurement results, bandwidths of 60 MHz (1.525 to 1.585 GHz) bandwidth for GPS band, 825 MHz (3.31 to 4.135 GHz) bandwidth for WiMAX band and 480 MHz (2.395 to 2.975 GHz) and 385 MHz (5.10 to 5.485 GHz) bandwidth for WLAN band were obtained on the basis of -10 dB. Also, gain and radiation pattern characteristics are measured and shown in the frequency of triple band as required.

Design of a Dual-Mode Planar Antenna Using a Reconfigurable Matching Network (재구성 정합 회로를 이용한 평판형 이중 모드 안테나 설계)

  • Kim, Yoon Geon;Kay, Youngchul;Choo, Hosung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.12
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    • pp.1337-1342
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    • 2012
  • In this paper, we propose a novel reconfigurable antenna that can change the electrical shape of the matching network using RF switches of PIN diodes. The designed antenna operates at two different modes that are Mode 1 (HSDPA band, 2.1~2.2 GHz) and Mode 2(WiBro WiFi band, 2.3~2.5 GHz). The antenna is built on both sides of a polyarcylate substrate. The measured reflection coefficient shows a matching bandwidth of 547 MHz($S_{11}$ <-3 dB, 2.035~2.582 GHz) for Mode 1 and 600 MHz($S_{11}$ <-3 dB, 2.2~2.8 GHz) for Mode 2, and it shows average vertical gains of -4.4 dBi and -4.5 dBi in x-y plane, respectively.

Implementation of Voltage Controlled Oscillator Using Planar Structure Split Ring Resonator (SRR) (평면형 구조의 분리형 링 공진기를 이용한 전압제어 발진기 구현)

  • Kim, Gi-Rae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.7
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    • pp.1538-1543
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    • 2013
  • In this paper, a novel split ring resonator is proposed for improvement of phase noise characteristics that is weak point of oscillator using planar type microstrip line resonator. Oscillator using proposed split ring resonator is designed, it has improved phase noise characteristics. At the fundamental frequency of 5.8GHz, 7.22dBm output power and -83.5 dBc@100kHz phase noise have been measured for oscillator with split ring resonator. The phase noise characteristics of oscillator is improved about 9.7dB compared to one using the general ${\lambda}/4$ microstrip resonator. Next, we designed voltage controlled oscillator using proposed split ring resonator with varactor diode. The VCO has 125MHz tuning range from 5.833GHz to 5.845GHz, and phase noise characteristic is -118~-115.5 dBc/Hz@100KHz. Due to its simple fabrication process and planar type, it is expected that the technique in this paper can be widely used for low phase noise oscillators for both MIC and MMIC applications.