• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.152-162
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• 2003

In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.4
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• pp.476-483
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• 2014

This paper describes the operational analysis results of the bipolar DC distribution system coupled with the distributed generators. The energy management for AC/DC power trade and the operational principle of distributed generators and energy storages were first analyzed by computer simulation with PSCAD/EMTDC software. After then a hardware simulator for the bipolar DC distribution system was built, which is composed of the grid-tied three-level inverter, battery storage, super-capacitor storage, and the voltage balancer. Various experiments with the hardware simulator were carried out to verify the operation of bipolar DC distribution system. The developed simulator has an upper-level controller which operates in connection with the controllers for each distributed generator and the battery energy storage based on CAN communication. The developed hardware simulator are possible to use in designing the bipolar DC distribution system and analyzing its performance experimentally.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.10
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• pp.1782-1789
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• 2008

This paper presents the design of acoustic resonance(AR) free and dimmable electronic ballast for 1kW Metal-Halide Lamp(MHL). The proposed Ballast consists of a Full-Bridge(FB) rectifier, a passive power factor correction(PFC) circuit, a full-bridge inverter, an ignitor using LC resonance and a control circuit for frequency modulation and dimming control. Whereas a passive PFC provides advantages in terms of high reliability and low cost for constructing the circuit, it is difficult to supply a stable voltage because of the output voltage ripple that occurs with a period of 120Hz. Although the ballast can be designed with a small size and a light weight if it is driven at a switching frequency between 1 and 100 kHz, AR will occur if the eigenvalue frequency of the lamp coincides with the inverter's operation frequency. The operation frequency was modulated in real time according to the output voltage ripple to compensate for the variation in power supplied to the lamp and eliminate AR. For dimming, the method, which modulated drive frequency of FB inverter using the control of DC level by microprocessor, was used. The Dimming ranged at least from 600W to 1kw as rated power of the lamp with 4 stages. Performance of the proposed technique was validated through numerical analysis, computer simulation using Pspice and by applying it to an electronic ballast for a prototype 1kW MHL.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.116-126
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• 1994

In this paper, the switch-level fault simulator for CMOS circuits with a gate-to-drain/source short fault is implemented. A fault model used in this paper is based on the graphical analysis of the electrical characteristics of the faulty MOS devices and the conversion of the faulty CMOS circuit to the equivalent faulty CMOS inverter in order to find its effect on the successive stage. This technique is very simple and has the increased accuracy of the simulation. The simulation result of the faulty circuit using the implemented fault simulator is compared with the result of the SPICE simulation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.4
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• pp.582-588
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• 2008

Microgrids are new distribution level power networks that consist of various electronically-interlaced generators and sensitive loads. The important control object of Microgrids is to supply reliable and high-quality power even during the faults or loss of mains(islanding) cases. This paper presents power control methods to coordinate multiple distributed generators(DGs) against abnormal cases such as islanding and load power variations. Using speed-droop and voltage-droop characteristics, multiple distributed generators can share the load power based on locally measured signals without any communications between them. This paper adopts the droop controllers for multiple DG control and improved them by considering the generation speed of distribution level generators. Dynamic response of the proposed control scheme has been investigated under severe operation cases such as islanding and abrupt load changes through PSCAD/EMTDC simulations.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.224-227
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• 2000

지금까지 멀티레벨 컨버터 및 인버터에 적용되어온 기존의 스너버는 턴온 스너버로 RLD 스너버 턴오프 스너버로 RCD 스너버를 사용하였으나 이들 RCD/RLD는 많은 소자를 필요로하며 스위칭시의 overvoltage와 스너버 손실이 큰 단점을 지니고 있다. 이와같은 문제점을 해결하기 위해 본 논문에서는 Diode-clamped 4-레벨 컨버터 및 인버터를 위한 새로운 스너버를 제안한다. 새로 제안하는 스너버는 Basic snubber unit로 특성이 좋은 Undeland 스너버와 수정된 RCD/RLD 스너버를 사용한다. 따라서 제안하는 스너버는 Undeland 스너버와 McMuray 스너버가 갖고 있는 특성 즉 사용소자의 수의 감소 과전압의 감소 스너버 손실의 감소 등과 좋은 특성을 지니고 있다 또한 본 논문에서 제안하는 4-레벨 컨버터 및 인버터를 위한 스너버 회로를 구성하는 방법은 다른 레벨의 멀티레벨 컨버터 및 인버터에도 적용가능하다,

• Journal of Power Electronics
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• v.10 no.4
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• pp.357-364
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• 2010

In this paper, a novel analysis of a carrier based PWM method for multilevel inverters is presented. The space vector PWM and carrier based PWM correlations in multilevel inverters are investigated in a nominal two-level switching diagram. The obtained results can be applied to design various carrier PWM techniques. In this paper, a carrier based single-state PWM technique, which reduces the switching number and optimizes the active voltage errors, is presented. This PWM technique can be advantageous if there are a large number of levels. The proposed method is mathematically formulated and demonstrated by simulations and experimental results.

• Proceedings of the KSR Conference
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• 2005.05a
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• pp.291-298
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• 2005

This paper describes the characteristic feather of propulsion system adopting mass production. The train formation is composed of 4 cars by 2 Motor cars and 2 Train cars. Acceleration rate must be 3.0 km/h/s or more when the car starts up to 35km/h by 16ton of passenger load. The system information supervision is easy because the system is controlled to perfect digital circuits, all information of an action is stored in a memory and is managed. The control system is composed of a fully digital circuit and a high level software such as C language. The DSP TMS320C31 is used for main processor and has the capability of 50MHz, 32bit floating point operation and has a C compiler. Therefore, the implementation of control algorithm and the change of function are easy. VVVF inverter using IGBT conducted variable combined test, environment test using chamber, interface test and field test etc.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.5B no.4
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• pp.358-365
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• 2005

In induction machine drive without a speed sensor, the estimation of the motor flux and speed often becomes deteriorated at low speeds with low back EMF. Our analysis shows that, in addition to the state resistance variation, the estimated value of field orientation angle is often corrupted by accumulative errors from the integration of voltage variables at motor terminals that have low signal/noise ratio at low frequencies. A repetitive loop path of integration in the feedback can amplify this type of error, thus speeding up the degradation process. The control system runs into information starvation due to the loss of correct field orientation. The machine's spiral vectors are controlled only in a reduced dimension in this situation. A novel control scheme is developed to improve the control performance of motor's current, torque and speed at low frequencies. The scheme gains a full-dimensional vector control and is less sensitive to the combined effect of the error sources at the low frequencies. Experimental tests demonstrate promising performances are achievable even below 0.5 Hz.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.5
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• pp.264-268
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• 1999

A new implementation strategy for the flux weakening control of a Surface Mounted Permanent Magnet Synchronous Motor (SPMSM) is proposed. It is implemented based on the output of the synchronous PI current regulator-reference voltage to PWM inverter. The onset of flux weakening and the level of the d-axis current are adjusted by the outer voltage regulation loop to prevent the saturation of the current regulator. The characteristics of this flux weakening scheme include no dependency on the machine parameters, the guarantee of current regulation on any operating condition, and fast transition into and out of the flux weakening mode. Experimental results at various operating conditions including 4-quadrant operation are presented to verify the feasibility of the proposed control scheme.