• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.4
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• pp.76-85
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• 2008

In this paper, a 800 MHz 1 W cartesian feedback linearized power amplifier is designed and fabricated for TETRA handset application. For amplification of TETRA signal with 200 kHz narrow bandwidth, amplifier linearization performance of more than 30 dBc is improved through the cartesian feedback linearizer at the offset Sequency of ${\pm}25$ kHz. It is clear that the linearization performance is affected by imbalance of gain and phase between I/Q signals and also DC offset. The linearization performance can be maximized by the compensation of those influences. Cartesian feedback is suitable for a liearization technique of narrow band signal with QAM and another modulation signals, as well.

• Current Optics and Photonics
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• v.2 no.2
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• pp.134-139
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• 2018

A novel approach for frequency-tripling vector signal generation via balanced detection without precoding and optical filter is proposed. The scheme is mainly utilizing an integrated dual-polarization quadrature phase shift keying (DPQPSK) modulator. In the DPQPSK modulator, one QPSK modulator is driven by an RF signal to generate high-order optical sidebands, while the other QPSK modulator is modulated by I/Q data streams to produce baseband vector signal as an optical carrier. After that, a frequency-tripling 16-quadrature-amplitude-modulation (16QAM) vector millimeter-wave (mm-wave) signal can be obtained by balanced detection. The proposed scheme can reduce the complexity of transmitter digital signal processing. The results show that, a 4 Gbaud baseband 16QAM vector signal can be generated at 30 GHz by frequency-tripling. After 10 km single-mode fiber (SMF) transmission, the constellation and eye diagrams of the generated vector signal perform well and a bit-error-rate (BER) below than 1e-3 can be achieved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.75-82
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• 2008

In this paper, we propose an efficient symbol detection algorithm for multiple-input multiple-output spatial multiplexing (MIMO-SM) systems and present its design and implementation results. By enhancing the performance of the first detected symbol which causes error propagation, the proposed algorithm achieves a considerable performance gain as compared to the conventional sorted QR decomposition (SQRD) based detection and the ordered successive detection (OSD) algorithms. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In case of 16QAM MIMO-SM system with 4 transmit and 4 receive ($4{\times}4$) antennas, at $BER=10^{-3}$ the proposed algorithm obtains the gai improvement of about 2.5-13.5 dB over the conventional algorithms. The proposed detection algorithm was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. The results show that the proposed algorithm can be implemented without increasing the hardware costs significantly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12C
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• pp.1044-1051
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• 2010

In this paper, we propose an efficient soft-output signal detection method for spatially multiplexed multiple input multiple output (MIMO) systems. The proposed method is based on the ordered successive interference cancellation (OSIC) algorithm, but it significantly improves the performance of the original OSIC algorithm by solving the error propagation problem. The proposed method combines this enhanced OSIC (ESIC) algorithm with a multiple ordering technique in a very efficient way. As a result, the log likelihood ratio (LLR) values can be computed by using a very small set of candidate symbol vectors. The proposed method has been implemented with a $0.13{\mu}m$ CMOS technology for a $4{\times}4$ 16-QAM MIMO system. The simulation and implementation results show that the proposed detector provides a very good solution in terms of performance and hardware complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5A
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• pp.496-503
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• 2010

The implementation of a RF transceiver for WRAN(Wireless Regional Area Network) system based on IEEE 802.22 standard using Cognitive Radio technology is presented in this paper. A CMOS RF transceiver IC for WRAN system operates in VHF/UHF(54~862MHz) broadband, and employs dual-path direct-conversion configuration and the in-band harmonic distortions are effectively suppressed by exploiting the dual-path direct conversion architecture. For 64QAM(3/4 coding rate) OFDM signal, an EVM of <-31.4dB(2.7%) has been achieved at 10dBm off-chip PA output power and the total chip area with pads is 12.95 mm2. The experimental results show that the proposed CMOS RF transceiver IC has perfect performance for WRAN system based on TDD(Time Division Duplex) mode.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.50-59
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• 2016

This work shows that the design and test results of a power amplifier(PA) with broadband and high linearity for 4G applications in $0.11{\mu}m$ CMOS process. A 1:2-transformer is designed for load impedance matching of PA and a inter-stage matching is implemented for a linearity. A designed PA achieves more than 27.3 dBm of linear output power and 26.1 % of power-added efficiency(PAE) under an adjacent channel leakage ratio(ACLR) of -30 dBc for a LTE 16-QAM 10 MHz signal with a carrier frequency range of 1.8 to 2.3 GHz.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.286-294
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• 2011

Cable modems typically are implemented by a forward error correction(FEC) scheme. The ITU-T Recommendation J-38 Annex B specifies using 64- and 256- quadrature amplitude modulation (QAM) and extended RS coding scheme. In implementing the cable modem, there are some problems to fabricate and fitting on FPGA chip. First, many clocks are needed in implementing cable modem because of different code rate and different modulation types. To reduce the number of clocks, we use the two memories, which are different clock speed for reading and writing data. Second, this system lost the bit-synchronization and frame-synchronization in decoder, the system recognize that all data is error. This paper solves the problems by using simple 5-stage registers and unique sync-word. Based on solutions for about problems, the cable modem is fabricated on FPGA chip name as Vertex II pro xc2vp30-5 by Xilinx, and we confirmed the effectiveness of the results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.11
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• pp.1043-1050
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• 2004

In this paper, Phase noise is analyzed and a novel approach of the nonlinear approximation including second order term of phase noise is presented to analyze and quantize system performance. As results, in QPSK-OFDM system, when PLL loop bandwidth is 5.0 Hz, 1.0 kHB, 0.5 kHz respectively, there are about 0.6 dB, 1.0 dB, 1.7 dB SNR penalties at BER=10$\^$-4/ compared with system without phase noise in AWGN channel. In 16QAM modulation, there are about 1.9 dB, 3.2 dB, 6.7 dB SNR penalties at BER=10$\^$-4/ respectively. At QPSK-OFDM system, comparing the previous linear approximation method with our proposed nonlinear approximation method, there is similar BER performance at phase noise variance lower than 0.02, but certain difference occurs as variance increases more than 0.02. Furthermore, analytical BER results closely match with simulation results in the OFDM system employing QPSK and 16qAM modulation. And, BER performance of QPSK-OFDM system is considerably degraded because of the BER error floor if the phase noise variance becomes larger than 0.03.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1749-1753
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• 2003

We proposed several systems for 1Giga bit Modem. The first, Binary ASK(Amplitude Shift Keying) system has a high speed shutter transmitter and no IF(Intermediate Frequency) receiver only by symbol synchronization. The advantage of proposed system is that circuitry is very simple without IF process. The disadvantage of proposed system are that line spectrum occurs interference to other channels, and enhancement to 4-level system is impossible due to its large SNR degradation. The second, Binary phase modulation system has a high speed shutter transmitter and IF-VCO(IF-Voltage Controlled Oscillator) control by base-band phase rotation. Polarity of shutter window is changed by the binary data. The window should be narrow same as above ASK. The advantage of proposed system is which error rate performance is superior. The disadvantage of proposed system are that Circuitry is more complex, narrow pull-in range of receiver caused by VCO and spectrum divergence by the non-linear amplifier. The third, 4-QAM(Quadrature Amplitude Modulation)system has a nyquist pulse transmitter and IF-VCO control by symbol clock. The advantage of proposed system are that signal frequency band is a half of 1GHz, reliable pull-in of VCO and possibility of double speed transmission(2Gbps) by keeping 1GHz frequency-band. The disadvantage of proposed system are that circuit complexity of pulse shaping and spectrum divergence by the non-linear amplifier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4C
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• pp.403-413
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• 2009

We compare three predistortion methods to prevent signal distortion and spectral re-growth due to the high PAPR (peak-to-average ratio) of OFDM signal and the non-linearity of high-power amplifiers. The three predistortion methods are pth order inverse, indirect learning architecture and look up table. The pth order inverse and indirect learning architecture methods requires less memory and has a fast convergence because these methods use a polynomial model that has a small number of coefficients. Nevertheless the convergence is fast due to the small number of coefficients and the simple computation that excludes manipulation of complex numbers by separate compensation for the magnitude and phase. The look up table method is easy to implement due to simple computation but has the disadvantage that large memory is required. Computer simulation result reveals that indirect learning architecture shows the best performance though the gain is less than 1 dB at $BER\;=\;10^{-4}$ for 64-QAM. The three predistorters are adaptive to the amplifier aging and environmental changes, and can be selected to the requirements for implementation.