• The Journal of the Korea institute of electronic communication sciences
• /
• v.14 no.3
• /
• pp.467-474
• /
• 2019

In this paper, we studied a method for a broadband stacked patch antenna structure which is widely used for bandwidth improvement. The characteristics according to the distance between the two patches were analyzed and the impedance matching was optimized by connecting parallel open stubs to the main patch feed line. The shunt matching stub is inserted underneath the parasitic patch and so it does not require additional space, which enables the proposed antenna structure to be advantageous in miniaturizing antenna. The effects of the various parameters on the antenna performance are examined, and we introduced the design procedure for the proposed antenna to operate in the frequency range of 2.3~2.7GHz. Experimental results show that the bandwidth of the proposed antenna is about 480MHz with 2.27~2.75GHz bandwidth. And the antenna gain was 5.8dBi at 2.3GHz and 7.8dBi at 2.6GHz within the bandwidth.

• Journal of the Microelectronics and Packaging Society
• /
• v.27 no.1
• /
• pp.17-24
• /
• 2020

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO₂ hybrid bonding.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.2
• /
• pp.43-51
• /
• 2014

In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

• Current Optics and Photonics
• /
• v.5 no.1
• /
• pp.23-31
• /
• 2021

We propose a wheel screen type Lamina 3D display, which realizes a 3D image that can satisfy the accommodation cue by projecting volumetric images encoded by varying polarization states to a multilayered screen. The proposed system is composed of two parts: an encoding part that converts depth information to states of polarization and a decoding part that projects depth images to the corresponded diffusing layer. Though the basic principle of Lamina displays has already been verified by previous studies, those schemes suffered from a bottleneck of inferior resolution of the 3D image due to the blurring on the surfaces of diffusing layers in the stacked volume. In this paper, we propose a new structure to implement the decoding part by adopting a form of the wheel screen. Experimental verification is also provided to support the proposed principle.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.545-546
• /
• 2008

This paper presents a low power CMOS low noise amplifier for UWB applications. To reduce the power consumption, two cascode amplifiers was stacked in DC. Designed with $0.18-{\mu}m$ CMOS technology, the proposed LNA achieves 20dB flat gain, below 3dB noise figure, and the power consumption of 5.2mW from a 1.8 V supply voltage.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.595-596
• /
• 2006

A novel Si via structure is suggested and fabricated for 3D MEMS package using the doped silicon as an interconnection material. Oxide isolations which define Si via are formed simultaneously when fabricating the MEMS structure by using DRIE and oxidation. Silicon Direct Bonding Multi-stacking process is used for stacked package, which consists of a substrate, MEMS structure layer and a cover layer. The bonded wafers are thinned by lapping and polishing. A via with the size of $20{\mu}m$ is fabricated and the electrical and mechanical characteristics of via are under testing.

• Proceedings of the Korean Society For Composite Materials Conference
• /
• 2005.04a
• /
• pp.71-75
• /
• 2005

For the damage tolerance improvement of conventional laminated composites, stitching process have been utilized for providing through-thickness reinforcements. 2D preforms were stacked with S-2 glass plain weave and S-2 glass MWK (Multi-axial Warp Knit) L type. 3D preforms were fabricated using the stitching process. All composite samples were fabricated by RTM (Resin Transfer Molding) process. To examine the damage resistance performance the low speed drop weight impact test has been carried out. For the assessment of damage after the impact loading, specimens were examined by scanning image. CAI (Compressive After Impact) tests were also conducted to evaluate residual compressive strength. Compared with 2D composites, the damage area of 3D composites was reduced by 20-30% and the CAI strength showed 5-10% improvement.

• Journal of Information Processing Systems
• /
• v.16 no.2
• /
• pp.343-359
• /
• 2020

In this paper, a new algorithm is proposed for three-dimensional (3D) shape recognition using local features of model views and its sparse representation. The algorithm starts with the normalization of 3D models and the extraction of 2D views from uniformly distributed viewpoints. Consequently, the 2D views are stacked over each other to from view cubes. The algorithm employs the descriptors of 3D local features in the view cubes after applying Gabor filters in various directions as the initial features for 3D shape recognition. In the training stage, we store some 3D local features to build the prototype dictionary of local features. To extract an intermediate feature vector, we measure the similarity between the local descriptors of a shape model and the local features of the prototype dictionary. We represent the intermediate feature vectors of 3D models in the sparse domain to obtain the final descriptors of the models. Finally, support vector machine classifiers are used to recognize the 3D models. Experimental results using the Princeton Shape Benchmark database showed the average recognition rate of 89.7% using 20 views. We compared the proposed approach with state-of-the-art approaches and the results showed the effectiveness of the proposed algorithm.

• Current Photovoltaic Research
• /
• v.7 no.1
• /
• pp.1-8
• /
• 2019

The $Cu(In,Ga)Se_2$ (CIGS) thin film obtained by two-step process (metal deposition and Se annealing) has a rough surface morphology and many voids at the CIGS/Mo interface. To solve the problem a precursor that contains Se was employer by depositing a (In,Se)/(Cu,Ga) stacked layer. We devised a two-step annealing (vacuum pre-annealing and Se annealing) for the precursor because direct annealing of the precursor in Se environment resulted in the small grains with unwanted demarcation between stacked layers. After vacuum pre-annealing up to $500^{\circ}C$ the CIGS film consisted of CIGS phase and secondary phases including $In_4Se_3$, InSe, and $Cu_9(In,Ga)_4$. The secondary phases were completely converted to CIGS phase by a subsequent Se annealing. A void-free CIGS/Mo interface was obtained by the two-step annealing process. Especially, the CIGS film prepared by vacuum annealing $450^{\circ}C$ and subsequent Se annealing $550^{\circ}C$ showed a densely-packed grains with smooth surface, well-aligned bamboo grains on the top of the film, little voids in the film, and also little voids at the CIGS/Mo interface. The smooth surface enhanced the cell performance due to the increase of shunt resistance.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.220-220
• /
• 2012

The supercapacitors with extraordinarily high capability for energy storage are attracting growing attention for their potential applications in portable electronic equipments, hybrid vehicles, cellular devices, and so on. The nanostructuring of the electrode surface can provide large surface area and consequently easy diffusion of ions in the capacitors. In addition, compared to two-dimensional nanostructures, the three-dimensional (3D) nano-architecture is expected to lead to significant enhancement of mechanical and electrical properties such as capacitance per unit area of the electrode. Polyaniline (PANi) is known as promising electrode material for supercapacitors due to its desirable properties such as high electro activity, high doping level and environmental stability. In this context, we fabricated well-ordered 3D PANi nanostructures on 3D polystyrene (PS) nanospheres which was arrayed by layer-by-layer stacking method. The height of the PANi nanostructures could be controlled by the number of PS layers stacked. 3D PANi hollow nanospheres were also fabricated by dissolving inner PS nanospheres, which resulted in further enhancement of the surface area and capacitance of the electrode.