• Journal of Advanced Navigation Technology
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• v.25 no.1
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• pp.68-77
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• 2021

In this paper, a GPS/MEMS IMU integrated navigation receiver module capable of operating in a high dynamic environment is designed and fabricated, and the results is confirmed. The designed module is composed of RF receiver unit, inertial measurement unit, signal processing unit, correlator, and navigation S/W. The RF receiver performs the functions of low noise amplification, frequency conversion, filtering, and automatic gain control. The inertial measurement unit collects measurement data from a MEMS class IMU applied with a 3-axis gyroscope, accelerometer, and geomagnetic sensor. In addition, it provides an interface to transmit to the navigation S/W. The signal processing unit and the correlator is implemented with FPGA logic to perform filtering and corrrelation value calculation. Navigation S/W is implemented using the internal CPU of the FPGA. The size of the manufactured module is 95.0×85.0×.12.5mm, the weight is 110g, and the navigation accuracy performance within the specification is confirmed in an environment of 1200m/s and acceleration of 10g.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2443-2450
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• 2014

In the motion recognition system using depth image, the depth image is converted to the real world formed 3D point cloud data for efficient algorithm apply. And then, output depth image is converted by the projective world after algorithm apply. However, when coordinate conversion, rounding error and data loss by applied algorithm are occurred. In this paper, when convert 3D point cloud data to depth image, we proposed efficient conversion method and its hardware implementation without rounding error and data loss according image size change. The proposed system make progress using the OpenCV and the window program, and we test a system using the Kinect in real time. In addition, designed using Verilog-HDL and verified through the Zynq-7000 FPGA Board of Xilinx.

• Journal of Power Electronics
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• v.11 no.4
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• pp.401-407
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• 2011

In order to enhance torque density of five-phase permanent magnetic synchronous motor with third harmonic injection for electric vehicles (EVs) applications, optimum seeking method for injection ratio of third harmonic was proposed adopting theoretical derivation and finite element analysis method, under the constraint of same amplitude for current and air-gap flux. By five-dimension space vector decomposition, the mathematic model in two orthogonal space plane, $d_1-q_1$ and $d_3-q_3$, was deduced. And the corresponding dual-plane vector control method was accomplished to independently control fundamental and third harmonic currents in each vector plane. A five-phase PMSM prototype with quasi-trapezoidal flux pattern and its fivephase voltage source inverter were designed. Also, the dual-plane vector control was digitized in a single XC3S1200E FPGA. Simulation and experimental results prove that using the proposed optimum seeking method, the torque density of five-phase PMSM is enhanced by 20%, without any increase of power converter capacity, machine size and iron core saturation.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.363-366
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• 2001

LILI-128 스트림 암호는 IMT-2000 무선단말간 데이터 암호화를 위하여 제안된 128-비트 크기의 스트림 암호방식이며, 클럭 조절형태의 채택에 따라 속도저하라는 구조적인 문제점을 안고 있다. 본 논문에서는 귀환/이동에 있어서 랜덤한 4개의 연결 경로를 갖는 4-비트병렬 $LFSR_{d}$를 제안함으로서 속도문제를 해결하였다. 그리고 ALTERA 사의 FPGA 소자(EPF10K20RC240-3)를 선정하여 그래픽/VHDL 하드웨어 구현 및 타이밍 시뮬레이션을 실시하였으며, 50MHz 시스템 클럭에서 안정적인 50Mbps (즉, 45 Mbps 수준인 T3급 이상, 설계회로의 최대 지연 시간이 20ns 이하인 조건) 출력 수열이 발생될 수 있음을 확인하였다. 마지막으로, FPGA/VHDL 설계회로를 Lucent ASIC 소자 ($LV160C,\;0.13{\mu}m\;CMOS\;&\;1.5v\;technology$)로 설계 변환 및 타이밍 시뮬레이션한 결과 최대 지연시간이 1.8ns 이하였고, 500 Mbps 이상의 고속화가 가능함을 확인하였다.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.837-840
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• 2005

This paper presents 3D graphics lighting processor based on vector processing using pipeline chaining. The lighting process of 3D graphics rendering contains many arithmetic operations and its complexity is very high. For high throughput, proposed processor uses pipelined functional units. To implement fully pipelined architecture, we have to use many functional units. Hence, the number of functional units is restricted. However, with the restricted number of pipelined functional units, the utilization of the units is reduced and a resource reservation problem is caused. To resolve these problems, the proposed architecture uses vector processing using pipeline chaining. Due to its pipeline chaining based architecture, it can perform 4.09M vertices per 1 second with 100MHz frequency. The proposed 3D graphics lighting processor is compatible with OpenGL ES API and the design is implemented and verified on FPGA.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.12
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• pp.1193-1200
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• 2016

In this paper, we developed a system for measuring a passive intermodulation distortion signal of the mobile communication RF module having a wide band characteristic. The Broadband was designed to represent the characteristics of the receiver to meet the low noise characteristics and wideband characteristics in the RF receiver were to represent a wide dynamic range(high dynamic range)from the RF receiving end. PIMD designed passive intermodulation distortion signal measured by applying the FPGA / DSP in the system was measured to record the program on the PC. Variable up to 650MHz-2700MHz showed up to-138dBc measured PIMD3.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.44 no.3
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• pp.212-217
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• 2016

The S-band receiver for Low Earth Orbit satellite is designed and fabricated as engineering model. Demodulator is implemented by using FPGA for extension of demodulator method. The receiver consists of RF Block, Digital demodulator and Power stage and has a Doppler tracking function to compensate a frequency shift that occur on the operation. The measured results of fabricated receiver show BER of less than $1.0{\times}10^{-6}$ at -110dBm RF input power and equipped a frequency tracking of ${\pm}100KHz$ relative to the center frequency. TID test was satisfied with the results of the test criterion is 10krad.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.877-880
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• 2005

As DMB, 3D game, Internet and movie is serviced for the recent mobile devices, high resolution display devices beyond VGA become used. Implementation of real-time moving pictures of 30렌 by software programming is difficult because the performance of mobile processors is not so high. The full frame moving picture can be supported by using specific hardware. In this paper, an OLED controller that is consists of flash memory controller and OLED interface is proposed for real-time moving picture on mobile displays. The proposed OLED controller is implemented in FPGA and the performance is evaluated.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.703-705
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• 2016

In this paper, we developed a wideband PIMD system to measure passive intermodulation distortion signals of mobile communication RF passive module. To represent wideband characteristic, we designed a receiver that meets low-noise and wideband characteristics in RF receiver. It allows high dynamic range in the RF receiver front end. In designed passive intermodulation distortion measurement system, we programed to display a PIMD signal with FPGA/DSP at PC. Implemented PIMD system was variable from 650 MHz to 2700 MHz and show up to -138 dB minimum detectable $3^{rd}$ passive inetrmodulation distortion signal.