• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3C
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• pp.287-294
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• 2010

MB-OFDM UWB system will adopt LDPC codes to enhance the decoding performance with higher data rates. In this paper, we will consider algorithm and architecture of the LDPC codes in MB-OFDM UWB system. To suggest the hardware efficient LDPC decoder architecture, LLR(log-likelihood-ration) calculation algorithms and check node update algorithms are analyzed. And we proposed the architecture of LDPC decoder for the high throughput application of Wimedia UWB. We estimated the feasibility of the proposed architecture by implementation in a FPGA. The implementation results show our architecture attains higher throughput than other result of QC-LDPC case. Using this architecture, we can implement LDPC decoder for high throughput transmission, but it is 0.2dB inferior to the BP algorithm.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.3
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• pp.110-117
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• 2014

This paper reports a depth-adaptive sharpness adjustment algorithm for stereoscopic perception improvement, and presents its field-programmable gate array (FPGA) implementation results. The first step of the proposed algorithm was to estimate the depth information of an input stereo video on a block basis. Second, the objects in the input video were segmented according to their depths. Third, the sharpness of the foreground objects was enhanced and that of the background was maintained or weakened. This paper proposes a new sharpness enhancement algorithm to suppress visually annoying artifacts, such as jagging and halos. The simulation results show that the proposed algorithm can improve stereoscopic perception without intentional depth adjustments. In addition, the hardware architecture of the proposed algorithm was designed and implemented on a general-purpose FPGA board. Real-time processing for full high-definition stereo videos was accomplished using 30,278 look-up tables, 24,553 registers, and 1,794,297 bits of memory at an operating frequency of 200MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.49-54
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• 2007

As digital contents based on 3D graphics are increased, the requirement for low power 3D graphic hardware for mobile devices is increased. We design a transformation engine for mobile 3D graphic processor. We propose a simplified transformation engine for mobile 3D graphic processor. The area of the transformation engine is reduced by merging a mapping transformation unit into a projective transformation unit and by replacing a clipping unit with a selection unit. It consists of a viewing transformation unit a projective transformation unit a divide by w nit, and a selection unit. It can process 32 bit floating point format of the IEEE-754 standard or a reduced 24 bit floating point format. It has a pipelined architecture so that a vertex is processed every 4 cycles except for the initial latency. The RTL code is verified using an FPGA.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.6
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• pp.55-61
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• 2013

In this paper, we describe design and implementation of audio encoder/decoder for voice synthesis. It uses the encoding of difference value of successive samples instead of the original sample value. and has the compression ratio of 4. The function is verified by using FPGA and the performance is measured by the fabricated chip using $0.35{\mu}m$ standard CMOS process. The system clock is 16.384MHz. The measured THD+n is from -40dB to -80dB with frequency variation and the power consumption is about 80mW. It is suited for the mobile application of high audio quality and low power consumption.

• Journal of electromagnetic engineering and science
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• v.16 no.4
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• pp.199-205
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• 2016

We present a novel schematic using a 3-dB coupler to transmit radiofrequency (RF) power to two receivers selectively. Whereas previous multiple receiver supporting schemes used hardware-switched methods, our scheme uses a soft power-allocating method, which has the advantage of variable power allocation in real time to each receiver. Using our scheme, we can split the charging area and focus the RF power on the targeted areas. We present our soft power-allocating method in three main points. First, we propose a new power distribution hardware structure using a FPGA (field-programmable gate array) and a 3-dB coupler. It can reconfigure the transmitting power to two receivers selectively using accurate FPGA-controlled signals with the aid of software. Second, we propose a power control method in our platform. We can variably control the total power of transmitter using the DC bias of the drain input of the amplifier. Third, we provide the possibility of expansion in multiple systems by extending these two wireless power transfer systems. We believe that this method is a new approach to controlling power amplifier output softly to support multiple receivers.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2006.11a
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• pp.37-40
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• 2006

3DTV는 아나로그 TV 및 HDTV의 차세대 이슈로 부상하였다. 그러나 대부분의 컨텐츠가 2D로 획득되어 저장되어 있으므로 2D 컨텐츠의 3D로의 변화이 필수적이다. MPEG 및 JVT에서 표준화가 진행되고 있으며 이를 위해 국내외 연구소, 학교, 및 업계가 관심을 가지고 참여하고 있다. 2D/3D 변환은 오래전부터 연구되어 왔으나 실제 응용에서는 기대에 못 미치고 있다. 본 논문에서는 FPGA에 기반하고 VHDL로 코딩하여 2D/3D 변환을 위한 Convolution filter를 적용하였다. 좌우 영상을 생성하기 위하여 Convolution filter로 좌우 영상을 왜곡하였다. 필터의 사용으로 사용자의 위치나 취향에 따라서 영상의 왜곡을 달리하여 효과의 변화를 줄 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.85-95
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• 2008

Characteristically, 3D graphic algorithms have to perform complex calculations on massive amount of stream data. The vertex and pixel shaders have enabled efficient execution of graphic algorithms by hardware, and these graphic processors may seem to have achieved the aim of "hardwarization of software shaders." However, the hardware shaders have hitherto been evolving within the limits of Z-buffer based algorithms. We predict that the ultimate model for future graphic processors will be an algorithm-independent integrated shader which combines the functions of both vertex and pixel shaders. We design the register file model that supports 3-dimensional computer graphic on the programmable unified shader processor. we have verified the accurate calculated value using FPGA Virtex-4(xcvlx200) made by Xilinx for operating binary files made by the implementation progress based on synthesis results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.59-70
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• 2007

In this paper, we proposed an effective T&L(Transform & Lighting) Processor architecture for a real time 3D graphics acceleration SoC(System on a Chip) in a mobile system. We designed Floating point arithmetic IPs for a T&L processor. And we verified IPs using a SoC Platform. Designed T&L Processor consists of 24 bit floating point data format and 16 bit fixed point data format, and supports the pipeline keeping the balance between Transform process and Lighting process using a parallel computation of 3D graphics. The delay of pipeline processing only Transform operation is almost same as the delay processing both Transform operation and Lighting operation. Designed T&L Processor is implemented and verified using a SoC Platform. The T&L Processor operates at 80MHz frequency in Xilinx-Virtex4 FPGA. The processing speed is measured at the rate of 20M Vertexes/sec.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.355-362
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• 2013

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.1
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• pp.351-357
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• 2013

Two cameras which function like human eyes, are needed to make 3D stereoscopic image. That is, stereoscopic image is made via 3 dimensional image processing for combining two images from left and right camera. In this paper two high resolution zoom cameras are used to make HD resolution stereoscopic camera. And the algorithm which convert to stereoscopic image from HD resolution zoom camera image, is implemented using FPGA for real-time operation. The algorithm which measure the depth of object between left and right image is proposed.