• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2023-2030
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• 2010

In this paper, we present research results of developing high performance scan conversion unit and implementing it on FPGA chip. To increase performance of scan conversion unit, we propose an architecture of scan converter that is a SIMD architecture and uses tile-based traversing method. The proposed scan conversion unit can operate about 124Mhz clock frequency on Xilinx Vertex4 LX100 device. To verify the scan conversion unit, we also develop shader unit, texture mapping unit and $240{\times}320$ color TFT-LCD controller to display outputs of the scan conversion unit on TFT-LCD. Because the scan conversion unit implemented on FPGA has 311Mpixels/sec pixel rate, it is applicable to desktop pc's 3d graphics system as well as mobile 3d graphics system needing high pixel rates.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of Broadcast Engineering
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• v.8 no.4
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• pp.452-464
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• 2003

In this paper, a multi-view 3D video processor was designed and implemented with several FPGAs for real-time applications. The 3D video processor receives 2D images from cameras (up to 16 cameras) and converts then to 3D video format for space-multiplexed 3D display. It can cope with various arrangements of 3D camera systems (or pixel arrays) and resolutions of 3D display. Tn order to verify the functions of 3D video Processor. some evaluation-board were made with five FPGAs.

• Journal of radiological science and technology
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• v.36 no.2
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• pp.157-163
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• 2013

Multileaf collimators whose Pb leaves are moving in two-dimensional directions have been used. We propose a different concept three-dimensional (3D) collimator with 3D shape that is automatically changeable to modulate the radiation dose even for complex tumors in real time. A voxel collimator, including a hinged Pb plane and a 3D assembly of many voxel collimators, was used. In each frame rotation axis, a motor, which was controlled by a circuit with field-programmable gate array (FPGA) board connected with computer, was operated according to a predetermined plan. Simulations of that, which are generally used for planning, were performed and compared with experimental results.

• Journal of Digital Contents Society
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• v.6 no.3
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• pp.169-174
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• 2005

In this paper we propose efficient design and implementation of JPEG image display board that can display JPEG image on TV. we used NAND Flash Memory to save the compressed JPEG bit stream and video encoder to display the decoded JPEG mage on TV. Also we convert YCbCr to RGB to super impose character on JPEG image. The designed B/D is implemented using FPGA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.279-282
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• 2012

In this paper, a hardware architecture of phase calculator for 3D image processing is proposed. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. Phase calculator designed in Verilog HDL is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification.

• Journal of Broadcast Engineering
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• v.19 no.5
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• pp.616-626
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• 2014

In this paper, we introduce a real-time stereo-to-multiview conversion system using FPGA and GPU. The system is based on two different devices so that it consists of two major blocks. The first block is a disparity estimation block that is implemented on FPGA. In this block, each disparity map of stereoscopic video is estimated by DP(dynamic programming)-based stereo matching. And then the estimated disparity maps are refined by post-processing. The refined disparity map is transferred to the GPU device through USB 3.0 and PCI-express interfaces. Stereoscopic video is also transferred to the GPU device. These data are used to render arbitrary number of virtual views in next block. In the second block, disparity-based view interpolation is performed to generate virtual multi-view video. As a final step, all generated views have to be re-arranged into a single image at full resolution for presenting on the target autostereoscopic 3D display. All these steps of the second block are performed in parallel on the GPU device.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.11a
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• pp.220-223
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• 2012

본 논문에서는 스테레오 영상으로부터 무안경 3D 디스플레이를 위한 다시점 영상을 생성하는 시스템을 제안한다. 제안한 시스템에서는 먼저 비디오 캡쳐 카드를 통해 입력되는 스테레오 영상으로부터 FPGA 상에서 구현된 Trellis 동적 프로그래밍 기법에 의해 좌우 변이 영상을 실시간으로 추출한다. 이 변이 영상을 기반으로 좌우 영상 사이에서 중간 시점 영상을 생성한다. 이렇게 추출된 좌우 변이 영상과 좌우 스테레오 영상은 각각 USB 3.0 과 PCI-express 인터페이스를 통해 GPU 로 전송되고, GPU 에서는 이들 데이터를 사용하여 변이 기반 영상 합성 방법을 통해 다시점 영상을 생성한다. 생성된 다시점 영상은 다시점 3 차원 디스플레이 규격에 맞게 재배치되어 재생된다.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.315-316
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• 2012

Three-level neutral point clamping (NPC) converter has been widely applied in high power drive system. And in this paper, a novel method is proposed to realize this algorithm based on FPGA, And the system is consist of two parts, the DSP part and FPGA part, the DSP part includes the control algorithms and the FPGA part works to generate and putout 12 PWM pulses. And the system is tested and verified using both simulation and experimentation.

• Journal of IKEEE
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• v.19 no.3
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• pp.335-341
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• 2015

Recently a demand for high precision absolute position transducer is increasing in order to control thickness in steel industry. LVDT (linear variable differential transformer) is widely used to measure the absolute position in the linearly moving cylinder under poor factory environment. In this paper we implement the three phase LVDT with a high resolution of one micron and L/D (LVDT to digital) converter. First we designed U, V, and W three phase signaling using FPGA. Second a pulse output algorithm is designed for position information with A and B phase waveforms. Finally the performance is compared with previous sensors. Experiments show that the linearity deviation error is 0.009788 [mm] and the average sinusoidal THD is 0.0751%, which means 2.2% and 33% more improved result than the previous sensors respectively.