• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3A
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• pp.265-271
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• 2009

This paper proposes an efficient initial frequency estimator for Digital Video Broadcasting-Second Generation (DVB-S2). The initial frequency offset of the DVB-S2 is around ${\pm}5MHz$, which corresponds to 20% of the symbol rate at 25Msps. To estimate a large initial frequency offset, the algorithm which call provide a large estimation range is required. Through the analysis of the data-aided (DA) algorithms, we find that the Mengali and Moreli (M&M) algorithm can estimate a large initial frequency offset at low SNR. Since the existing frequency estimator based on M&M algorithm has a high hardware complexity, we propose the methods to reduce the hardware complexity of the initial frequency estimator. This can be achieved by reducing the number of autocorrelators and arctangents. The proposed architecture can reduce the hardware complexity about 64.5% compared to the existing frequency estimator and has been thoroughly verified on the Xilinx Virtex II FPGA board.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.62-70
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• 2011

Nowadays image sensor is an essential component in many multimedia devices, and it is covered by a color filter array to filter out specific color components at each pixel. We need a certain algorithm to combine those color components reconstructed a full color image from incomplete color samples output from an image sensor, which is called a demosaicking process. Most existing demosaicking algorithms are developed for ideal image sensors, but they do not work well for the practical cases because of dissimilar characteristics of each sensor. In this paper, we propose a new demosaicking algorithm in which the color filter characteristics are fully utilized to generate a good image. To demonstrate significance of our algorithm, we used a commerically available sensor, CBN385B, which is a sort of Honeycomb-style CFA(Color Filter Array) CCD image sensor. As a performance metric of the algorithm, PSNR(Peak Signal to Noise Ratio) and RGB distribution of the output image are used. We first implemented our algorithm in C-language for simulation on various input images. As a result, we could obtain much enhanced images whose PSNR was improved by 4~8 dB compared to the commonly idealized approaches, and we also could remove the inclined red property which was an unique characteristics of the image sensor(CBN385B).Then we implemented it in hardware to overcome its problem of computational complexity which made it operate slow in software. The hardware was verified on Spartan-3E FPGA(Field Programable Gate Array) to give almost the same performance as software, but in much faster execution time. The total logic gate count is 45K, and it handles 25 image frmaes per second.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.110-119
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• 2017

This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a field-programmable gate array (FPGA) integrated module. The CIS is composed of a $320{\times}240$ pixel array with $3.2{\mu}m{\times}3.2{\mu}m$ pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a $0.11-{\mu}m$ CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.

• Nuclear Engineering and Technology
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• v.55 no.8
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• pp.2873-2878
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• 2023

The purpose of this study is to perform radiation monitoring by acquiring gamma images and real-time optical images for ^99mTc vial source using charge couple device (CCD) cameras equipped with the proposed compact gamma camera. The compact gamma camera measures 86×65×78.5 mm³ and weighs 934 g. It is equipped with a metal 3D printed diverging collimator manufactured in a 45 field of view (FOV) to detect the location of the source. The circuit's system uses system-on-chip (SoC) and field-programmable-gate-array (FPGA) to establish a good connection between hardware and software. In detection modules, the photodetector (multi-pixel photon counters) is tiled at 8×8 to expand the activation area and improve sensitivity. The gadolinium aluminium gallium garnet (GAGG) measuring 0.5×0.5×3.5 mm³ was arranged in 38×38 arrays. Intrinsic and extrinsic performance tests such as energy spectrum, uniformity, and system sensitivity for other radioisotopes, and sensitivity evaluation at edges within FOV were conducted. The compact gamma camera can be mounted on unmanned equipment such as drones and robots that require miniaturization and light weight, so a wide range of applications in various fields are possible.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.14-23
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• 2002

Two implementation methods for SOVA (Soft Output Viterbi Algorithm)of Turbo decoder are applied and verfied. The first method is the combination of a trace back (TB) logic for the survivor state and a double trace back logic for the weight value in two-step SOVA. This architecure of two-setp SOVA decoder allows important savings in area and high-speed processing compared with that of one-step SOVA decoding using register exchange (RE) or trace-back (TB) method. Second method is adjusting the reliability value with a scaling factor between 0.25 and 0.33 in order to compensate for the distortion for a rate 1/3 and 8-state SOVA decoder with a 256-bit frame size. The proposed schemes contributed to higher SNR performance by 2dB at the BER 10E-4 than that of SOVA decoder without a scaling factor. In order to verify the suggested schemes, the SOVA decoder is testd using Xillinx XCV 1000E FPGA, which runs at 33.6MHz of the maximum speed with 845 latencies and it features 175K gates in the case of 256-bit frame size.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.9
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• pp.1095-1102
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• 2016

In this paper, we propose a decoding scheme that can apply to a three dimensional turbo product code(TPC) with a single parity check code(SPC). In general, SPC is used an axis with shortest code length in order to maximize a code rate of the TPC. However, SPC does not have any error correcting capability, therefore, the error correcting capability of the three-dimensional TPC results in little improvement in comparison with the two-dimensional TPC. We propose two schemes to improve performance of three dimensional TPC decoder. One is $min^*$-sum algorithm that has advantages for low complexity implementation compared to Chase-Pyndiah algorithm. The other is a modified serial iterative decoding scheme for high performance. In addition, the simulation results for the proposed scheme are shown and compared with the conventional scheme. Finally, we introduce some practical considerations for hardware implementation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.3
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• pp.157-163
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• 2019

A small millimeter-wave tracking radar is a pulse radar that searches, detects, and tracks a target in real time through a TWS (Track While Scan) method on a sea-going traps target with a large RCS running at low speed. This paper describes the development of a simulated signal generator to verify the performance of a small millimeter wave tracking radar in laboratory anechoic chamber environment. We describe a GUI program for testing and performance analysis in conjunction with hardware configuration and tracking radar, and verified the simulated signal generator implemented through performance test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.26-36
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• 2006

In this paper, we propose a cost-effective color filter may (CFA) demosaicing method for digital still cameras in which a single CCD or CMOS image sensor is used. Since a CFA is adopted, we must interpolate missing color values in the red, green and blue channels at each pixel location. While most state-of-the-art algorithms invest a great deal of computational effort in the enhancement of the reconstructed image to overcome the color artifacts, we focus on eliminating the color artifacts with low computational complexity. Using spatial correlation of the adjacent pixels, the edge-directional information of the neighbor pixels is used for determining the edge direction of the current pixel. We apply our method to the state-of-the-art algorithms which use edge-directed methods to interpolate the missing color channels. The experiment results show that the proposed method enhances the demosaiced image qualify from $0.09{\sim}0.47dB$ in PSNR depending on the basis algorithm by removing most of the color artifacts. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 12K, and five line memories are used.

• Proceedings of the KOSOMBE Conference
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• v.1998 no.11
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• pp.299-300
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• 1998

Recently the development of medical modality like as MRI, 3D US, DR etc is very active. Therefore it is more required not only the enhancement of quality in medical service but the improvement of medical system based on quantization, minimization, and optimization of high speed. Especially, as the changing into the digital modality system, it gets to start using ASIC(Application Specific Integrated Circuit) to realize one board system. It requires the implementation of hardware debugging and effective speedy algorithm with more speed and accuracy in order to support and replace existing device. If objected image could be linked to high speed process board with special interface and pre-processed using FPGA, it can be used in real time image processing and protocol of HIS(Hospital Information System). This study can support the basic circuit design of medical image board which is able to realize image processing basically using digitalized medical image, and to interface between existing device and image board containing image processing algorithm.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.688-698
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• 2018

Quasi Z-Source Multilevel Inverter (QZMLI) topology has attracted grid connected Photovoltaic (PV) systems in recent days. So there is a remarkable research thrust in switching techniques and control strategies of QZMLI. This paper presents the mathematical analysis of Phase shift- Pulse Width Amplitude Modulation (PS-PWAM) for QZMLI and emphasizes on the advantages of the technique. The proposed technique uses the maximum and minimum envelopes of the reference waves for generation of pulses and proportion of it to generate shoot-through pulses. Hence, it results in maximum utilization of input voltage, lesser switching loss, reduced Total Harmonic Distortion (THD) of the output voltage, reduced inductor current ripple and capacitor voltage ripple. Due to these qualities, the QZMLI with PS-PWAM emerges to be the best suitable for PV based grid connected applications compared to Phase shift-Pulse Width Modulation (PS-PWM). The detailed math analysis of the proposed technique has been disclosed. Simulation has been performed for the proposed technique using MATLAB/Simulink. A prototype has been built to validate the results for which the pulses were generated using FPGA /SPARTAN 3E.