• 마이크로전자및패키징학회지
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• 제20권2호
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• pp.47-51
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• 2013

본 연구에서는 웨이퍼 레벨 Cu 본딩을 이용한 3D 적층 IC의 개발을 위해 2단계 기계적 화학적 연마법(CMP)을 제안하고 그 결과를 고찰하였다. 다마신(damascene) 공정을 이용한 $Cu/SiO_2$ 복합 계면에서의 Cu dishing을 최소화하기 위해 Cu CMP 후 $SiO_2$ CMP를 추가로 시행하였으며, 이를 통해 Cu dishing을 $100{\sim}200{\AA}$까지 낮출 수 있었다. Cu 범프의 표면거칠기도 동시에 개선되었음을 AFM 관찰을 통해 확인하였다. 2단 CMP를 적용하여 진행한 웨이퍼 레벨 Cu 본딩에서는 dishing이나 접합 계면이 관찰되지 않아 2단 CMP 공정이 성공적으로 적용되었음을 확인할 수 있었다.

• 마이크로전자및패키징학회지
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• 제24권4호
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• 대한금속재료학회지
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• 제50권10호
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• pp.775-783
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• 2012

The effect of thermal annealing on the in-situ growth characteristics of intermetallics (IMCs) and the mechanical strength of Cu pillar/Sn-3.5Ag microbumps are systematically investigated. The $Cu_6Sn_5$ phase formed at the Cu/solder interface right after bonding and grew with increased annealing time, while the $Cu_3Sn$ phase formed at the $Cu/Cu_6Sn_5$ interface and grew with increased annealing time. IMC growth followed a linear relationship with the square root of the annealing time due to a diffusion-controlled mechanism. The shear strength measured by the die shear test monotonically increased with annealing time. It then changed the slope with further annealing, which correlated with the change in fracture modes from ductile to brittle at a critical transition time. This is ascribed not only to the increasing thickness of brittle IMCs but also to the decreasing thickness of the solder, as there exists a critical annealing time for a fracture mode transition in our thin solder-capped Cu pillar microbump structures.

• 대한금속재료학회지
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• 제49권2호
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• pp.180-186
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• 2011

Isothermal annealing and electromigration tests were performed at $125^{\circ}C$ and $125^{\circ}C$, $3.6{\times}10_4A/cm^2$ conditions, respectively, in order to compare the growth kinetics of the intermetallic compound (IMC) in the Cu/thin Sn/Cu bump. $Cu_6Sn_5$ and $Cu_3Sn$ formed at the Cu/thin Sn/Cu interfaces where most of the Sn phase transformed into the $Cu_6Sn_5$ phase. Only a few regions of Sn were not consumed and trapped between the transformed regions. The limited supply of Sn atoms and the continued proliferation of Cu atoms enhanced the formation of the $Cu_3Sn$ phase at the Cu pillar/$Cu_6Sn_5$ interface. The IMC thickness increased linearly with the square root of annealing time, and increased linearly with the current stressing time, which means that the current stressing accelerated the interfacial reaction. Abrupt changes in the IMC growth velocities at a specific testing time were closely related to the phase transition from $Cu_6Sn_5$ to $Cu_3Sn$ phases after complete consumption of the remaining Sn phase due to the limited amount of the Sn phase in the Cu/thin Sn/Cu bump, which implies that the relative thickness ratios of Cu and Sn significantly affect Cu-Sn IMC growth kinetics.