• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.129-134
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• 2005

Electroplating copper is the important role in formation of 3D stacking interconnection in SiP (System in Package). The I-V characteristics curves are investigated at different electrolyte conditions. Inhibitor and accelerator are used simultaneously to investigate the effects of additives. Three different sizes of via are tested. All via were prepared with RIE (reactive ion etching) method. Via's diameter are 50, 75, $100{\mu}m$ and the height is $100{\mu}m$. Inside via, Ta was deposited for diffusion barrier and Cu was deposited fer seed layer using magnetron sputtering method. DC, pulse and pulse revere current are used in this study. With DC, via cannot be filled without defects. Pulse plating can improve the filling patterns however it cannot completely filled copper without defects. Via was filled completely without defects using pulse-reverse electroplating method.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.25-29
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• 2009

High temperature high humidity and thermal shock reliability tests were performed for the board level COB(chip-on-board) flip chip packages using self-formulated and commercial NCPs(non-conductive pastes) to ensure the performance of NCP flip chip packages. It was considered that the more smaller fused silica filler in prototype NCPs is more favorable for high temperature high humidity reliability. The failure of NCP interconnection was affected by the expansion of epoxy due to moisture absorption rather than the fatigue due to thermal stress. It was considered that the NCP having more higher adhesive strength seems to be more favorable to increase the thermal shock reliability.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.96-99
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• 2000

We presents a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and examined electrical parameters with a HP5475A TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3 $\times$ 3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, self inductance 146pH, mutual capacitance 10.9fF and mutual inductance 16.9pH. S parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55㎓ and the loss of 0.26dB. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1975-1984
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• 1997

In this paper, we analyzed the frequency characteristics and the crosstalk of the adjacent parallel lines and the crossed lines in high-speed packaging interconnections by using the three-dimensional finite difference time domain (3D FDTD) method. To analyze the actual crosstalk phenomena in the transmission of the high-speed digital sgnal, the step pulse with fast rise time was used for the source excitation signal instead of using the Gaussian pulse that is generally used in FDTD. To veify the theoretical resutls, the experimental interconnection lines that were fabricated on the Duroid substrate($\varepsilon_{r}$=2.33, h=0.787 [mm]) were tested by TDR(time domain reflectometry). The results show good agreement between the analyzed results and the tested outcomes.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.3
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• pp.475-482
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• 2019

In this paper, we propose a triple band antenna for GPS / DCS / WLAN system. The proposed antenna has the characteristics required by considering the interconnection of two strip lines and various slits on the ground place. The total substrate size is $31mm(W1){\times}50mm(L1)$, thickness (h) 1.6 mm, and the dielectric constant is 4.4, which is made of $22mm(W7+W12+W8){\times}43mm(L4+L3)$ antenna size on the FR-4 substrate. From the fabrication and measurement results, bandwidths of 340 MHz (1.465 to 1.805 GHz), 480 MHz (2.155 to 2.635 GHz) and 1950 MHz (4.975 to 6.925 GHz) were obtained on the basis of -10 dB. Also, gain and radiation pattern characteristics are measured and shown in the frequency triple band as required.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.1
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• pp.31-38
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• 2020

In this paper, we propose a quadruple band antenna for GPS/WLAN/WiMAX application. The proposed antenna has quadruple band characteristics by considering the interconnection of four strip lines and DGS on the ground place. The total substrate size is 20.0 mm (W1) ⨯27.0 mm (L1), thickness (h) 1.0 mm, and the dielectric constant is 4.4, which is made of 20.0 mm (W2)⨯ 27.0 mm (L8 + L6+ L10) antenna size on the FR-4 substrate. From the fabrication and measurement results, bandwidths of 60 MHz (1.525 to 1.585 GHz) bandwidth for GPS band, 825 MHz (3.31 to 4.135 GHz) bandwidth for WiMAX band and 480 MHz (2.395 to 2.975 GHz) and 385 MHz (5.10 to 5.485 GHz) bandwidth for WLAN band were obtained on the basis of -10 dB. Also, gain and radiation pattern characteristics are measured and shown in the frequency of triple band as required.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.8 s.111
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• pp.732-738
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• 2006

Divide-by-2 and divide-by-4 circuits which can operate up to 10 GHz are designed. A design method used in these circuits is the TSPC(True Single Phase Clocking) topology. The structure of the TSPC dividers is very simple because they need only a single clock and purely consist of smalt sized cmos devices. Through measurements, we find the fact that in proportion to the bias voltage, the free running frequency increases and the operation region also moves toward a higher frequency region. For operating conditions of bias voltage $3.0{\sim}4.0V$, input power 16dBm and dcoffset $1.5{\sim}2.0V$, 5 GHz and 2.5 GHz output signals divided by 2 and 4 are measured. The layout size of the divide-by-2 circuit is about $500{\times}500 um^2$($50{\times}40um^2$ except pad interconnection part).

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• Journal of the Microelectronics and Packaging Society
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• v.24 no.2
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• pp.11-15
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• 2017

As the heat dissipation problem is increased in 3D multi flip chip packages, an improvement of thermal conductivity in bonding interfaces is required. In this study, the effect of alumina filler addition was investigated in non-conductive paste(NCP). The fine alumina filler having average particles size of 400 nm for the fine pitch interconnection was used. As the alumina filler content was increased from 0 to 60 wt%, the thermal conductivity of the cured product was increased up to 0.654 W/mK at 60 wt%. It was higher value than 0.501 W/mK which was reported for the same amount of silica. It was also found out that the addition of fine sized alumina filler resulted in the smaller decrease in thermal conductivity than the larger sized particles. The viscosity of NCP with alumina addition was increased sharply at the level of 40 wt%. It was due to the increase of the interaction between the filler particles according to the finer particle size. In order to achieve the appropriate viscosity and excellent thermal conductivity with fine alumina fillers, the highly efficient dispersion process was considered to be important.

• Journal of Advanced Navigation Technology
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• v.26 no.2
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• pp.99-104
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• 2022

Recently, the domestic demand for weapon systems based on aircraft platforms is gradually increasing. In particular, the demand for effective precision guided missile(PGM) which cruises for several hundred kilometers after launch to strike the ground target is rising drastically, but it is in the early stages of development, and research based on it are limited. This paper is a study on the power converter unit(PCU) within PGM which is mounted on an aircraft platform based on MIL-STD-1760, which is an interface between an aircraft and PGM. We investigated the electrical properties and structure of the umbilical connector, and the aircraft/store electrical interconnection system. Also, the focus on the design specifications of the PCU that supplies power were described. This result 3 phase AC input, which is the state for the guided simulation power supply in the state of being mounted on an aircraft that rectification method with power factor correction(PFC) compared to bridge rectifier circuit. In the future, it may be used as a basis for power supply design on aircraft mounted weapon systems.