• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.595-595
• /
• 2012

현재 대부분의 태양전지는 약 90% 이상이 si을 기판으로 제작되고 있다. Solar cell의 효율을 감소시키는 원인은 여러 가지가 있다. bulk life time 감소, 수분침투, 우박, 바람에 의한 영향들이 태양전지 효율을 감소시킨다. 모듈에 눈이 쌓이거나 바람이 불어 외부적 힘이 가해져 micro crack 가게 된다면 전체 모듈은 과부하와 발열 현상이 일어나고 interconnection 감소로 인하여 효율도 떨어지게 된다. 본 연구에서는 평균적인 효율이 17.5%, 크기가 6인치 단결정 태양전지에 일정 간격으로 힘을 가하여 파라미터 변화를 측정하였다. 두께가 $250{\mu}m$인 cell에 0.8lb에 힘을 가했을 때 cell이 파괴 되는 것을 알 수 있었다. 힘을 가해줄 수록 Voc와 Isc가 감소하는 경향성을 보였고 결국에 효율도 감소하였다. 또한 ANSYS 시뮬레이션을 사용하여 셀에 힘이 가해졌을 때 어떤 변화가 생기는 지 확인하였다. 시뮬레이션을 통하여 셀에 힘이 가해졌을 때 힘의 분포도, bowing 현상을 3D 그래프로 나타내었다. 힘이 세기가 강해질수록 bowing 현상은 심해졌고 힘의 분포도도 달라졌다.

• ETRI Journal
• /
• v.36 no.4
• /
• pp.617-624
• /
• 2014

Through-silicon via (TSV) technology provides much of the benefits seen in advanced packaging, such as three-dimensional integrated circuits and 3D packaging, with shorter interconnection paths for homo- and heterogeneous device integration. In TSV, a destructive cross-sectional analysis of an image from a scanning electron microscope is the most frequently used method for quality control purposes. We propose a quantitative evaluation method for TSV etch profiles whereby we consider sidewall angle, curvature profile, undercut, and scallop. A weighted sum of the four evaluated parameters, nominally total score (TS), is suggested for the numerical evaluation of an individual TSV profile. Uniformity, defined by the ratio of the standard deviation and average of the parameters that comprise TS, is suggested for the evaluation of wafer-to-wafer variation in volume manufacturing.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.1
• /
• pp.99-104
• /
• 2013

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional integration circuit(IC) cannot be a solution for the enhancement of the semiconductor integration circuit technology due to an increase in RC delay among interconnects. To address this problem, a new technology of 3 dimensional integration circuit (3D-IC) has been developing. In this study, three-dimensional integrated device was investigated due to improve of reducing the size, interconnection problem, high system performance and functionality.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.3
• /
• pp.37-41
• /
• 2012

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

• Journal of Ocean Engineering and Technology
• /
• v.36 no.3
• /
• pp.181-193
• /
• 2022

This study presents a mission management technique that is a key component of underwater docking system used to expand the operating range of autonomous underwater vehicle (AUV). We analyzed the docking scenario and AUV operating environment, defining the feasible initial area (FIA) level, event level, and global path (GP) command to improve the rate of docking success and AUV safety. Non-holonomic constraints, mounted sensor characteristic, AUV and mission state, and AUV behavior were considered. Using AUV and docking station, we conducted experiments on land and at sea. The first test was conducted on land to prevent loss and damage of the AUV and verify stability and interconnection with other algorithms; it performed well in normal and abnormal situations. Subsequently, we attempted to dock under the sea and verified its performance; it also worked well in a sea environment. In this study, we presented the mission management technique and showed its performance. We demonstrated AUV docking with this algorithm and verified that the rate of docking success was higher compared to those obtained in other studies.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.4
• /
• pp.101-112
• /
• 2004

In this paper, we developed a numerical analysis model by using ADI-FDTD method to analyze three-dimensional interconnect structure. We discretized maxwell's curl equation by using ADI-FDTD. Using ADI-FDTD method, a sampler circuit designed from 3.3 V CMOS technology is simplified to 3-metal line structure. Using this simplified structure, the time delay and signal distortion of complex interconnects are investigated. As results of simulation, 5∼10 ps of delay time and 0.1∼0.2 V of signal distortion are measured. As demonstrated in this paper, the full-wave analysis using ADI-FDTD exhibits a promise for accurate modeling of electromagnetic phenomena in high-speed VLSI interconnect.

• Journal of KIISE:Computer Systems and Theory
• /
• v.30 no.7_8
• /
• pp.381-386
• /
• 2003

In this paper, we consider the problem of embedding complete binary trees into 3-dimensional meshes. The method of embedding a complete binary tree into 3-dimensional mesh with the link congestion two is considered in [1], and the embedding in [2] shows that a complete binary tree can be embedded into a ,3-dimensional mesh of expansion 1.27. The proposed embedding in this paper shows that a complete binary tree can be embedded into a 3-dimensional mesh of expansion approximately 1.125 with the link congestion one, using the dimensional ordered routing. Such method yields some improved features in terms of minimizing the link congestion or the expansion of embedding comparing to the previous results.

• Korean Journal of Metals and Materials
• /
• v.48 no.11
• /
• pp.1028-1034
• /
• 2010

In the development of 3D package, through silicon via (TSV) formation technology by using deep reactive ion etching (DRIE) is one of the key processes. We performed the Bosch process, which consists of sequentially alternating the etch and passivation steps using $SF_6$ with $O_2$ and $C_4F_8$ plasma, respectively. We investigated the effect of changing variables on vias: the gas flow time, the ratio of $O_2$ gas, source and bias power, and process time. Each parameter plays a critical role in obtaining a specified via profile. Analysis of via profiles shows that the gas flow time is the most critical process parameter. A high source power accelerated more etchant species fluorine ions toward the silicon wafer and improved their directionality. With $O_2$ gas addition, there is an optimized condition to form the desired vertical interconnection. Overall, the etching rate decreased when the process time was longer.

• Korean Journal of Optics and Photonics
• /
• v.23 no.1
• /
• pp.12-16
• /
• 2012

In the paper, we fabricated a Ni master with $45^{\circ}$-mirror structures for flexible waveguide fabrication. The flexible waveguide films with embedded $45^{\circ}$-angled mirrors at the waveguide ends were successfully fabricated using a UV-imprint process. Next, in order to enhance the reflectivity of the mirrors, Ni(3 nm)-Au(200 nm) bilayers were evaporated on the $45^{\circ}$-angled facets through a locally opened thin mask using an electron beam evaporator. We measured propagation loss, bending loss, mirror loss and bending reliability of the fabricated waveguide.

• Journal of Power Electronics
• /
• v.11 no.3
• /
• pp.360-368
• /
• 2011

This paper proposes an active frequency with a positive feedback in the d-q frame anti-islanding method suitable for a robust phase-locked loop (PLL) algorithm using the FFT concept. In general, PLL algorithms for grid-connected PV PCS use d-q transformation and controllers to make zero an imaginary part of the transformed voltage vector. In a real grid system, the grid voltage is not ideal. It may be unbalanced, noisy and have many harmonics. For these reasons, the d-q transformed components do not have a pure DC component. The controller tuning of a PLL algorithm is difficult. The proposed PLL algorithm using the FFT concept can use the strong noise cancelation characteristics of a FFT algorithm without a PI controller. Therefore, the proposed PLL algorithm has no gain-tuning of a PI controller, and it is hardly influenced by voltage drops, phase step changes and harmonics. Islanding prediction is a necessary feature of inverter-based photovoltaic (PV) systems in order to meet the stringent standard requirements for interconnection with an electrical grid. Both passive and active anti-islanding methods exist. Typically, active methods modify a given parameter, which also affects the shape and quality of the grid injected current. In this paper, the active anti-islanding algorithm for a grid-connected PV PCS uses positive feedback control in the d-q frame. The proposed PLL and anti-islanding algorithm are implemented for a 250kW PV PCS. This system has four DC/DC converters each with a 25kW power rating. This is only one-third of the total system power. The experimental results show that the proposed PLL, anti-islanding method and topology demonstrate good performance in a 250kW PV PCS.