• Title/Summary/Keyword: 300[mm] Wafer

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The Formation of the Shallow Junction by RTD and Characteristic Analysis for $n^+$ -p Diode with Ti-silicide (고속 열 확산에 의한 얕은 접합 형성과 Ti-실리시이드화된 $n^+$ -p 다이오드 특성 분석)

  • 최동영;이성욱;주정규;강명구;윤석범;오환술
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.8
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    • pp.80-90
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    • 1994
  • The ultra shallow junction was formed by 2-step RTP. Phosphorus solid source(P$_{2}O_{5}$) was transfered on wafer surface during RTG(Rapid Thermal Glass Transfer) of which process condition was 80$0^{\circ}C$ and 60sec. The process temperature and time of the RTD(Rapid Thermal Diffusion) were 950~105$0^{\circ}C$ during 5~15sec respectively sheet resistances were measured as 175~320$\Omega$/m and junction depth and dopth and dopant surface concentration were measured as 0.075~0.18$\mu$m and 5${\times}10^{19}cm^{4}$ respectively. Ti-silicide was formed by 2-step RTA after 300$\AA$ Titanium was deposited. The 1st RTA (2nd RTA) was carried out at the temperature of $600^{\circ}C$(700~80$0^{\circ}C$) for 30 seconds (10~60 seconds) under N$_2$ ambient. Sheet resistances after 2nd RTA were measured as 46~63$\Omega$/D. Si/Ti component ratio was evaulated as 1.6~1.9 from Auger depth profile. Ti-Silicided n-p junction diode (pattern size : 400$\times$400$\mu$m) was fabricated under the RTD(the process was carried out at the temperature of 100$0^{\circ}C$ for 10seconds) and 2nd RTA(theprocess was carried out at the temperature of 750$^{\circ}C$ for 60 seconds). Leakage current was measured 1.8${\times}10^{7}A/mm^{2}$ at 5V reverse voltage. Whent the RTD process condition is at the temperature of 100$0^{\circ}C$ for 10seconds and the 2nd RTA process condition is at the temperature of 75$0^{\circ}C$ for 60 seconds leakage current was 29.15${\times}10^{9}A$(at 5V).

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백색 LED증착용 MOCVD 유도가열 장치에서 가스 inlet위치에 따른 기판의 온도 균일도 측정

  • Hong, Gwang-Gi;Yang, Won-Gyun;Ju, Jeong-Hun
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.08a
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    • pp.115-115
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    • 2010
  • 고휘도 고효율 백색 LED (lighting emitting diode)가 차세대 조명광원으로 급부상하고 있다. 백색 LED를 생산하기 위한 공정에서 MOCVD (유기금속화학증착)장비를 이용한 에피웨이퍼공정은 에피층과 기판의 격자상수 차이와 열팽창계수차이로 인하여 생성되는 에피결함의 문제로 기판과 GaN 박막층 사이에 완충작용을 해줄 수 있는 버퍼층 (Buffer layer)을 만든다. 그 위에 InGaN/GaN MQW (Multi Quantum Well)공정을 하여 고휘도 고효율 백색 LED를 구현 할 수 있다. 이 공정에서 기판의 온도가 불균일해지면 wafer 파장 균일도가 나빠지므로 백색 LED의 yield가 떨어진다. 균일한 기판 온도를 갖기 위한 조건으로 기판과 induction heater의 간격, 가스의 흐름, 기판의 회전, 유도가열코일의 디자인 등이 장비의 설계 요소이다. 본 연구에서는 유도가열방식의 유도가열히터를 이용하여 기판과 히터의 간격에 차이에 따른 기판 균일도 측정했고, 회전에 의한 기판의 온도분포와 자기장분포의 실험적 결과를 상용화 유체역학 코드인 CFD-ACE+의 모델링 결과와 비교 했다. 또한 가스의 inlet위치에 따른 기판의 온도 균일도를 측정하였다. 본 연구에서 사용된 가열원은 유도가열히터 (Viewtong, VT-180C2)를 사용했고, 가열된 흑연판 표면의 온도를 2차원적으로 평가하기 위하여 적외선 열화상 카메라 (Fluke, Ti-10)를 이용하여 온도를 측정했다. 와전류에 의한 흑연판의 가열 현상을 누출 전계의 분포로 확인하기 위하여 Tektronix사의 A6302 probe와 TM502A amplifier를 사용했다. 흑연판 위에 1 cm2 간격으로 211곳에서 유도 전류를 측정했다. 유도전류는 벡터양이므로 $E{\theta}$를 측정했으며, 이때의 측정 방향은 흑연판의 원주방향이다. 또한 자기장에 의한 유도전류의 분포를 확인하기 위하여 KANETEC사의 TM-501을 이용하여 흑연판 중심으로부터 10 mm 간격으로 자기장을 측정 했다. 저항 가열 히터를 통하여 대류에 의한 온도 균일도를 평가한 결과 gap이 3 mm일때, 평균 온도 $166.5^{\circ}C$에서 불균일도 6.5%를 얻었으며, 회전에 의한 온도 균일도 측정 결과는 2.5 RPM일 때 평균온도 $163^{\circ}C$에서 5.5%의 불균일도를 확인했다. 또한 CFD-ACE+를 이용한 모델링 결과 자기장의 분포는 중심이 높은 분포를 나타냄을 확인했고, 기판의 온도분포는 중심으로부터 55 mm되는 곳에서 300 W/m3로 가장 높은 분포를 나타냈다. 가스 inlet 위치를 흑연판 중심으로 수직, 수평 방향으로 흘려주었을 때의 불균일도는 각각 10.5%, 8.0%로 수평 방향으로 가스를 흘려주었을 때 2.5% 온도 균일도 향상을 확인했다.

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Boron Doping Method Using Fiber Laser Annealing of Uniformly Deposited Amorphous Silicon Layer for IBC Solar Cells (IBC형 태양전지를 위한 균일하게 증착된 비정질 실리콘 층의 광섬유 레이저를 이용한 붕소 도핑 방법)

  • Kim, Sung-Chul;Yoon, Ki-Chan;Kyung, Do-Hyun;Lee, Young-Seok;Kwon, Tae-Young;Jung, Woo-Won;Yi, Jun-Sin
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.456-456
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    • 2009
  • Boron doping on an n-type Si wafer is requisite process for IBC (Interdigitated Back Contact) solar cells. Fiber laser annealing is one of boron doping methods. For the boron doping, uniformly coated or deposited film is highly required. Plasma enhanced chemical vapor deposition (PECVD) method provides a uniform dopant film or layer which can facilitate doping. Because amorphous silicon layer absorption range for the wavelength of fiber laser does not match well for the direct annealing. In this study, to enhance thermal affection on the existing p-a-Si:H layer, a ${\mu}c$-Si:H intrinsic layer was deposited on the p-a-Si:H layer additionally by PECVD. To improve heat transfer rate to the amorphous silicon layer, and as heating both sides and protecting boron eliminating from the amorphous silicon layer. For p-a-Si:H layer with the ratio of $SiH_4$ : $B_2H_6$ : $H_2$ = 30 : 30 : 120, at $200^{\circ}C$, 50 W, 0.2 Torr for 30 minutes, and for ${\mu}c$-Si:H intrinsic layer, $SiH_4$ : $H_2$ = 10 : 300, at $200^{\circ}C$, 30 W, 0.5 Torr for 60 minutes, 2 cm $\times$ 2 cm size wafers were used. In consequence of comparing the results of lifetime measurement and sheet resistance relation, the laser condition set of 20 ~ 27 % of power, 150 ~ 160 kHz, 20 ~ 50 mm/s of marking speed, and $10\;{\sim}\;50 {\mu}m$ spacing with continuous wave mode of scanner lens showed the correlation between lifetime and sheet resistance as $100\;{\Omega}/sq$ and $11.8\;{\mu}s$ vs. $17\;{\Omega}/sq$ and $8.2\;{\mu}s$. Comparing to the singly deposited p-a-Si:H layer case, the additional ${\mu}c$-Si:H layer for doping resulted in no trade-offs, but showed slight improvement of both lifetime and sheet resistance, however sheet resistance might be confined by the additional intrinsic layer. This might come from the ineffective crystallization of amorphous silicon layer. For the additional layer case, lifetime and sheet resistance were measured as $84.8\;{\Omega}/sq$ and $11.09\;{\mu}s$ vs. $79.8\;{\Omega}/sq$ and $11.93\;{\mu}s$. The co-existence of $n^+$layeronthesamesurfaceandeliminating the laser damage should be taken into account for an IBC solar cell structure. Heavily doped uniform boron layer by fiber laser brings not only basic and essential conditions for the beginning step of IBC solar cell fabrication processes, but also the controllable doping concentration and depth that can be established according to the deposition conditions of layers.

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Application of CMP Process to Improving Thickness-Uniformity of Sputtering-deposited CdTe Thin Film for Improvement of Optical Properties (스퍼터링 증확 CdTe 박막의 두께 불균일 현상 개선을 위한 화학적기계적연마 공정 적용 및 광특성 향상)

  • Park, Ju-Sun;Lim, Chae-Hyun;Ryu, Seung-Han;Myung, Kuk-Do;Kim, Nam-Hoon;Lee, Woo-Sun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.375-375
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    • 2010
  • CdTe as an absorber material is widely used in thin film solar cells with the heterostructure due to its almost ideal band gap energy of 1.45 eV, high photovoltaic conversion efficiency, low cost and stable performance. The deposition methods and preparation conditions for the fabrication of CdTe are very important for the achievement of high solar cell conversion efficiency. There are some rearranged reports about the deposition methods available for the preparation of CdTe thin films such as close spaced sublimation (CSS), physical vapor deposition (PVD), vacuum evaporation, vapor transport deposition (VTD), closed space vapor transport, electrodeposition, screen printing, spray pyrolysis, metalorganic chemical vapor deposition (MOCVD), and RF sputtering. The RF sputtering method for the preparation of CdTe thin films has important advantages in that the thin films can be prepared at low growth temperatures with large-area deposition suitable for mass-production. The authors reported that the optical and electrical properties of CdTe thin film were closely connected by the thickness-uniformity of the film in the previous study [1], which means that the better optical absorbance and the higher carrier concentration could be obtained in the better condition of thickness-uniformity for CdTe thin film. The thickness-uniformity could be controlled and improved by the some process parameters such as vacuum level and RF power in the sputtering process of CdTe thin films. However, there is a limitation to improve the thickness-uniformity only in the preparation process [1]. So it is necessary to introduce the external or additional method for improving the thickness-uniformity of CdTe thin film because the cell size of thin film solar cell will be enlarged. Therefore, the authors firstly applied the chemical mechanical polishing (CMP) process to improving the thickness-uniformity of CdTe thin films with a G&P POLI-450 CMP polisher [2]. CMP process is the most important process in semiconductor manufacturing processes in order to planarize the surface of the wafer even over 300 mm and to form the copper interconnects with damascene process. Some important CMP characteristics for CdTe were obtained including removal rate (RR), WIWNU%, RMS roughness, and peak-to-valley roughness [2]. With these important results, the CMP process for CdTe thin films was performed to improve the thickness-uniformity of the sputtering-deposited CdTe thin film which had the worst two thickness-uniformities of them. Some optical properties including optical transmittance and absorbance of the CdTe thin films were measured by using a UV-Visible spectrophotometer (Varian Techtron, Cary500scan) in the range of 400 - 800 nm. After CMP process, the thickness-uniformities became better than that of the best condition in the previous sputtering process of CdTe thin films. Consequently, the optical properties were directly affected by the thickness-uniformity of CdTe thin film. The absorbance of CdTe thin films was improved although the thickness of CdTe thin film was not changed.

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