• 한국산업융합학회 논문집
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• 제24권4_1호
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• pp.377-385
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• 2021

High voltage direct current(HVDC) systems has been an alternative method of a power transmission to replace high voltage alternate current(HVAC), which is a traditional AC transmission method. Due to technical limitations, Line commutate converter HVDC(LCC-HVDC) was mainly used. However, result from many structural problems of LCC-HVDC, the voltage source converter HVDC(VSC-HVDC) are studied and applied recently. In this paper, after analyzing the reactive power and output voltage ripple, which are the main problems of LCC-HVDC, the characteristics of each HVDC are summarized. Based on this result, a new LCC-HVDC structure is proposed by combining LCC-HVDC with the MMC structure, which is a representative VSC-HVDC topology. The proposed structure generates lower reactive power than the conventional method, and greatly reduces the 12th harmonic, a major component of output voltage ripple. In addition, it can be easily applied to the already installed LCC-HVDC. When the proposed method is applied, the control of the reactive power compensator becomes unnecessary, and there is an advantage that the cut-off frequency of the output DC filter can be designed smaller. The validity of the proposed LCC-HVDC is verified through simulation and experiments.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 추계학술대회 논문집
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• pp.249-250
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• 2012

해상 풍력 발전은 가장 유망한 재생 에너지원의 하나이며, 육상 풍력 발전보다 풍력이 강력하고 일정하여 장시간 고출력 발생이 가능하다. 또한 소음, 공간적 한계, 경관훼손 등 기존 육상 풍력 발전의 단점을 보완하고 초대형 단지조성이 가능한 장점이 있다. 초대형 해상풍력단지에는 일반적으로 MW급의 해상풍력발전기가 사용된다. 본 논문에서는 MW급의 해상 풍력발전기에 ANPC(Active Neutral-Point-Clamped) Multi-Level VSC(Voltage Source Converter)를 적용하여 Back-to-Back으로 구성한 시스템을 제안하고 계통연계형 풍력 발전 시스템을 모의한 시뮬레이션을 통하여 제안된 시스템의 성능을 검증한다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2017년도 전력전자학술대회
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• pp.212-213
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• 2017

In this paper is presented a pre-charging sequence for single-phase cascaded neutal-point-clamped(NPC) converters for capacitors voltage balancing. capacitor imbalance problem in pre-charge sequence is caused in cascaded NPC converter by its topology. the DC link voltage at each NPC converter module can be balanced by the proposed switching method. the design and performance of the proposed sequence are verified by simulation and experimental results using prototype.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권2호
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• pp.235-245
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• 2014

This paper presents an envelope tracking power amplifier using a standard CMOS process for the 3GPP long-term evolution transmitters. An efficiency of the CMOS power amplifier for the modulated signals can be improved using a highly efficient and wideband CMOS bias modulator. The CMOS PA is based on a two-stage differential common-source structure for high gain and large voltage swing. The bias modulator is based on a hybrid buck converter which consists of a linear stage and a switching stage. The dynamic load condition according to the envelope signal level is taken into account for the bias modulator design. By applying the bias modulator to the power amplifier, an overall efficiency of 41.7 % was achieved at an output power of 24 dBm using the 16-QAM uplink LTE signal. It is 5.3 % points higher than that of the power amplifier alone at the same output power and linearity.

• 한국정보통신학회논문지
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• 제7권6호
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• pp.1283-1290
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• 2003

PWM Buck AC-AC 컨버터는 최근 들어 전압 또는 전력 레귤레이터, 전자식 변압기, 위상 천이기와 같은 산업현장의 다양한 응용분야에 폭넓게 사용되고 있다. 본 논문에서는 이러한 PWM Buck AC-AC 컨버터의 정적 및 동적 모델링과 완전한 특성 해석을 제시한다. 먼저, 3상의 컨버터 시스템은 DQ 변환 기법에 의하여 모델링 되고 그에 따라 전압이득과 역률과 같은 기본적인 특성식을 구하고 제어를 위한 시스템의 상태 방정식과 전달함수를 구한다. 다음으로, 이러한 해석에 기초하여 매우 빠른 동적 응답을 갖도록 순시적인 듀티 변동이 가능한 feedforward-feedback 제어기법을 제안한다. 끝으로, 실험결과를 통하여 이러한 모델링과 해석 및 제어가 유효함을 확인할 수 있다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.315-316
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• 2012

Three-level neutral point clamping (NPC) converter has been widely applied in high power drive system. And in this paper, a novel method is proposed to realize this algorithm based on FPGA, And the system is consist of two parts, the DSP part and FPGA part, the DSP part includes the control algorithms and the FPGA part works to generate and putout 12 PWM pulses. And the system is tested and verified using both simulation and experimentation.

• 전력전자학회논문지
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• 제21권5호
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• pp.373-380
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• 2016

In this paper, a 50-kW high-efficiency modular fast charger for both electric vehicle (EV) and neighborhood electric vehicle (NEV) is proposed. The proposed fast charger consists of five 10-kW modules to achieve fault tolerance, ease of thermal management, and reduce component stress. Three-level topologies for both AC-DC and DC-DC converters are employed to use 600V MOSFET, resulting in ease of component selection and increase in switching frequency. The proposed three-level DC-DC converter with coupled inductor and its hybrid switching method can reduce the circulating current under wide output voltage range. A 50-kW prototype of the proposed fast charger was developed and tested to verify the validity of the proposed concept. Experimental results show that the proposed fast charger achieves a rated efficiency of 95.2% and a THD of less than 3%.

• 전기학회논문지
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• 제65권10호
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• pp.1655-1663
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• 2016

Recently the researches on Modular Multi-level Converter (MMC) are being highlighted because high quality and efficient power transmission are key issues in the High Voltage Direct Current (HVDC) transmission system. This paper proposes an improved pre-charging method for the sub-module capacitors in MMC that operates in Nearest Level Control (NLC) modulation. The proposed method does not require additional circuits or Pulse Width Modulation (PWM) techniques. The feasibility of proposed method was verified through computer simulations for a scaled 3-phase 10kVA MMC with 12 sub-modules per each arm. Hardware experiments with a scaled prototype were performed in the lab to confirm the simulation results.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.949-952
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• 2000

A low power 10bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent ADC from increasing a FR excessively, but also to perform a high resolution at a single power supply of 3.3V The proposed ADC is implemented by a 0.6${\mu}$m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of ${\pm}$0.5LSB, an integral nonlinearity (INL) of ${\pm}$1.0LSB

• Journal of Power Electronics
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• 제18권6호
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• pp.1866-1878
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• 2018

This paper presents a neutral point deviation and ripple compensation control method for application to 3-level NPC converters. The neutral point deviation and its harmonic components are analyzed with a focus on the average current flowing through the neutral point of the dc-link. This paper also proposes a control scheme to compensate for the neutral point deviation and dominant harmonic components under generalized unbalanced grid operating conditions. The positive and negative sequence components of the pole voltages and ac input currents are employed to accurately explain the behavior of 3-level NPC converters. Simulation and experimental results are presented to verify the validity of the proposed method.