• 제목/요약/키워드: 3-level inverters

검색결과 90건 처리시간 0.026초

Simple Space Vector PWM Scheme for 3-level NPC Inverters Including the Overmodulation Region

  • Lee, Dong-Myung;Jung, Jin-Woo;Kwa, Sang-Shin
    • Journal of Power Electronics
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    • 제11권5호
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    • pp.688-696
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    • 2011
  • This paper proposes a simple space vector PWM (SVPWM) scheme including overmodulation operation for 3-level NPC (Neutral Point Clamped) Inverters. The proposed scheme features a simple decision and calculation procedure for determining switching times in the overmodulation range by utilizing the duty calculation method used in 2-level inverters and the minimum phase error projection method widely employed in motor drive systems. The proposed scheme does not need to detect the angle of the reference vector or calculate trigonometric functions to determine the magnitude of the voltage vector. The magnitude of the angle of the new reference voltage vector is decided in advance with the help of the Fourier Series Expansion to extend the linearity of the output voltage of 3-level inverters in the overmodulation region. Experimental results demonstrate the validity of the proposed SVPWM scheme including overmodulation operation for 3-level NPC inverters.

멀티레벨 인버터와 다상 유도기를 이용한 견인기용 대전력 VSI의 구조와 특성 (Configurations of High Power VSI Drives for Traction Applications Using Multi Level Inverters and Multi Phase Induction Motors)

  • ;류홍제;김종수;임근희
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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    • pp.500-504
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    • 1997
  • Current source inverter drives of auto sequentially commutated type are very popular in high power applications, because of simple power circuit configuration with four quadrant operation. But the six-step current output create harmonic problems and the input power factor of such a drive is not always good. In this respect pulse width modulated drives using gate turn off thyristors ( GTO ) are finding application, especially in traction drives. However the switching and snubber loses of a GTO do not permit the inverter switching frequency go beyond a few hundred hertz.This will again introduce low frequency harmonic problems. Multi level inverters of the 3-level and 5-level can be considered as an alternative to overcome the low switching frequency harmonic problem of the 2-level GTO inverters. But with multi level inverters the complexity of the power circuit increases. In this paper a combination of multi level ( 2-level and 3-level ) inverters and multi phase induction motor ( 3-phase and 6-phase) configurations are presented for high power VSI drives for traction applications with reduced inverter switching frequency requirements coupled with reduced voltage rating for the power switch.

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3-레벨 인버터 UPFC의 제어기설계와 동특성해석 (Controller Design and Dynamic Performance Analysis of UPFC based on 3-Level Inverters)

  • 한병문
    • 대한전기학회논문지:전력기술부문A
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    • 제49권6호
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    • pp.272-279
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    • 2000
  • This paper describes a controller design and dynamic performance analysis of UPFC based on 3-level inverters. Major attention is focused on the controller design for both shunt and series inverters, including regulator design for the dc link voltage sharing across the dc capacitors. An energy-based approach was investigated for effectively designing the controller. A detailed UPFC model has been developed with EMTP using 24-pulse 3-level inverters to verify this approach. Simulation results about dynamic performance of UPFC confirm effects for increasing transmission capacity and damping low-frequency oscillation. The developed simulation model would be very effective to analyze the dynamic performance of UPFC.

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3-레벨 인버터를 위한 과전압 제한회로 설계 (A Circuit Design for Clamping an Overvoltage in Three-level Inverters)

  • 정재훈;이요한;현동석
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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    • pp.299-301
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    • 1995
  • This paper represents an overvoltage clamping circuit for three level inverters. With a proposed overvoltage clamping circuit, the problems that high voltage stresses and voltage unbalance between outer and inner switches occurs in high power and high voltage 3-level inverters are reduced.

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미션 프로파일을 고려한 단상 5-레벨 태양광 NPC 인버터의 전력 반도체 소자 수명 분석 (Lifetime Evaluation of Power Devices of Single-Phase 5-Level NPC Inverters Considering Mission Profile of PV Systems)

  • 류태림;최의민
    • 전력전자학회논문지
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    • 제27권3호
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    • pp.221-227
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    • 2022
  • The reliability improvement of PV systems is an important factor in reducing the cost of PV energy because it is closely related to the annual energy production as well as the maintenance cost of PV systems. The reliability of PV inverters plays a key role in the reliability of PV systems because it is regarded as one of the most reliable critical parts of PV systems. The lifetime evaluation of PV inverters considering the mission profile in the design phase plays an important role in reliability design to ensure the required lifetime of PV inverters. In this paper, the lifetime of representative single-phase T-type and I-type NPC inverters are comparatively evaluated by considering the mission profile of a PV system recorded at Iza, Spain. Furthermore, the effect of the pulse width modulation methods on the lifetime is also discussed. The lifetime evaluation of PV inverters is performed at the component-level first and then the system level by considering all power devices.

3-레벨 NPC 인버터에서 보조 레그를 이용한 공통 모드 전압 제거 (Cancellation of Common-Mode Voltages in Three-Level NPC Inverters with Auxiliary Leg)

  • 리쿠억안;이동춘
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2016년도 전력전자학술대회 논문집
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    • pp.487-488
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    • 2016
  • In this paper, a new active circuit for common-mode voltage (CMV) cancellation in three-level NPC (neutral-point clamped) inverters is proposed, which can avoid the saturation of the common-mode transformer (CMT). The proposed circuit utilizes an additional three-level leg to produce the compensating CMV of the NPC inverters, which eliminates the CMV of the inverter through the CMT.

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3레벨 인버터로 구동되는 유도전동기 직접토크제어의 저속성능 개선 (An Improvement on low Speed Operation Performances of DTC for 3-level Inverter-fed Induction Motors)

  • 이교범;송중호;최익;김광배;유지윤
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제49권10호
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    • pp.693-700
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    • 2000
  • A direct torque control algorithm for 3-level inverter-fed induction motors is presented. Conventional voltage selection methods provoke some problems such as stator flux drooping phenomenon and undersirable torque control appeared especially at the low speed operation. To overcome these problems, a proposed method uses intermediate voltage vectors, which are inherently generated in 3-level inverters. In the proposed algorithm, both subdivision of the basic switching sectors and applications of tntermediated voltages improve the low speed operation characteristics. This algorithm basically considers applications in which direct torque controlled induction motors are fed by 3-level inverters with low switching frequency around 500Hz. An adaptive observer is also employed to bring better responses at the low speed operation, by estimating some state-variables, motor speed and motor parameters which take a deep effect on the performance of the low speed operation. Simulation and experiment results verify effectiveness of the proposed algorithm.

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3-레벨 T-형 및 NPC 인버터의 전력 손실 비교 분석 (Comparative Analysis of Power Losses for Three-Level T-Type and NPC PWM Inverters)

  • 알레미파얌;이동춘
    • 전력전자학회논문지
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    • 제19권2호
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    • pp.173-183
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    • 2014
  • In this paper, an analysis of power losses for the three-level T-type and neutral-point clamped (NPC) PWM inverters is presented, in which the conduction and switching losses of semiconductor devices of the inverters are taken into account. In the inverter operation, the conduction loss depends on the modulation index (MI) and power factor (PF), whereas the switching loss depends on the switching frequency. Power losses for the T-type and NPC inverters are analyzed and calculated at the different operating points of MI, PF and the switching frequency, in which the four different models of semiconductor devices are adopted. In the case of lower MI, the NPC-type is more efficient than the T-type, and vice versa. The validity of the power loss analysis has been verified by the simulation results.

양방향 스위치를 이용한 H-bridge 구조의 새로운 멀티레벨 인버터 (A New Multilevel Inverter of H-bridge Topology using Bidirection Switch)

  • 이상혁;강성구;이태원;허민호;박성준
    • 전력전자학회논문지
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    • 제17권4호
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    • pp.291-297
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    • 2012
  • Recently, Switching devices become cheaper, depending on the multi-level inverters are considered as the power-conversion systems for high-power and power-quality demanding applications. The multi-level inverters can reduce the THD(Total Harmonic Distortion) as the output which is similar sinusoidal waveform by synthesizing several capacitor DC voltages. However it has some disadvantages such as increased number of components, complex PWM control method. Therefore, this paper is proposed the new multi-level inverter topology using an new H-bridge output stage with a bidirectional auxiliary switch. The proposed topology is the 4-level 3-phase PWM inverter with less switching part than conventional multi-level inverters and reactive power control possible. In order to understand the new multi-level inverter, topology analysis and switching patterns and modes according to the current loop are described in this paper. The proposed multi-level inverter topology is validated through PSIM simulation and the experimental results are provided from a prototype.

NPC 3-레벨 인버터를 적용한 차세대 고속전철 IPMSM의 구동 (IPMSM Drives Using NPC 3-Level Inverters for the Next Generation High Speed Railway System)

  • 권순환;진강환;김성제;이태형;김윤호
    • 한국철도학회논문집
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    • 제15권2호
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    • pp.129-134
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    • 2012
  • NPC 멀티레벨 인버터는 2-레벨 인버터 방식에 비해 전력용 반도체 소자의 정격 전압과 출력전류의 고조파를 감소시킬 수 있는 장점이 있어 고압 대용량 전동기 구동시스템에 적합하다. NPC 3-레벨 인버터를 이용한 IPMSM의 속도 제어에서 일정 토크 영역에서는 최대 토크 제어, 일정 출력 영역에서는 약계자 제어 방식을 적용하였다. 제안된 시스템은 MATLAB/Simulink를 이용한 시뮬레이터를 구현하여 모의 시험 결과 분석을 통해 그 타당성을 검증하였다.