• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.11-19
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• 2015

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.1-9
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• 2010

Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• The KIPS Transactions:PartD
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• v.8D no.3
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• pp.193-202
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• 2001

Currently, the components of the GIS have been physically run on a stand-alone system. With rapid advances in internet technology, GIS users require that they are able to not only access they heterogeneous and remote GIS database as well as their own information, but also share them. However, these GIS have the defects that can not handle formats different from own data format. Therefore, in this paper, we propose to integrate the components of the heterogeneous and remote GIS using CORBA in order to solve these problems, which is a distributed object technology, the mediator and wrapper technology in client and server layers.

• IE interfaces
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• v.24 no.3
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• pp.248-257
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• 2011

The amount of Meta-data to be managed increases with development of information technology. However, when trying to integrate and share product information of heterogeneous systems within or between companies, sharing of information is impossible if product information classification systems are different. Due to the situation mentioned above, engineers judge the product information classification system and maps corresponding Meta-data for document-based sharing. Judging exponentially increasing amount of data by engineers and sharing product information using documents create great amount of time delay and errors in data handling. Therefore, construction of a system for integrated management and interoperability between product information based on semantic information similar to engineer's judgment is required. This paper proposes a methodology and necessity of a system for interoperability of product information based on semantic web, and also designs a system to integrate heterogeneous systems with different product information using rule based reasoning. This paper also suggests a system base for interoperability and integration of product information between heterogeneous systems by integrating the product information classification system semantically.

• Journal of the Korea Society of Computer and Information
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• v.29 no.3
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• pp.117-125
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• 2024

In this paper, implement and propose an Active Electronically Scanned Array (AESA) radar integration analysis system which specialized for radar development by using heterogeneous media. Most analysis systems are used to analyze and improve the cause of defects, so they help the test easier. However, previous log analysis systems that operate only based on text are not intuitive and difficult to find the information user want at once if there is a lot of log information. so when an equipment defect occurs, there are limitations in analyzing the cause of defect. Therefore, the analysis system in this paper utilizes heterogeneous media. The media defined in this paper refers to recording text-based data, displaying data as image or video and visualizing data. The proposed analysis system classifies and stores data that transmitted and received between radar devices, radar target detection and Tracking algorithm data, etc. also displays and visualizes radar operation results and equipment defect information in real time. With this analysis system, it can quickly provide information what user want and assistance in developing high quality radar.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.37-41
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• 2012

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

• ETRI Journal
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• v.36 no.4
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• pp.635-642
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• 2014

Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time.

• The KIPS Transactions:PartD
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• v.12D no.3 s.99
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• pp.365-374
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• 2005

The B2B electronic product commerce needs intermediary system to provide an integrated interface for the parts libraries of multiple suppliers. However, it is difficult to automatically integrate the parts libraries because they are heterogeneous. Existing ontology-based approaches show a limited functionality of automated integration of information because Dey can not prevent ontologies from being modeled in different ways, so that the inter-ontology mappings to resolve the heterogeneity become complicated and arbitrary. In order to overcome such problems this paper proposes an ontology modeling framework for parts libraries based on the Guarino's theory of upper ontology. The framework provides knowledge modeling primitives which have explicit formal meanings and modeling principles based on ontological natures. Using the framework, ontology developers can model the knowledge of parts libraries systematically and consistently, so that the resulting ontologies become comparable and uniform and the ontology merging algorithm for the automated information integration can be easily developed.

• The KIPS Transactions:PartD
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• v.11D no.3
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• pp.519-532
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• 2004

With the explosion of bioinformatics data such proteins and genes, biologists need a integrated system to analyze and organize large datasets that interact with heterogeneous types of biological data. In this paper, we propose a integration system based on a mediated data warehouse architecture using a XML model in order to combine protein related data at biology laboratories. A fact constellation model in this system is used at a common model for integration and an integrated schema it translated to a XML schema. In addition, to track source changes and provenance of data in an integrated database employ incremental update and management of sequence version. This paper shows modeling of integration for protein structures, sequences and classification of structures using the proposed system.