• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.5
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• pp.682-687
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• 2022

In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.530-538
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• 2007

An inductor library for efficient low cost RFIC design has been developed based on a standard digital 0.18 ${\mu}m$ CMOS process. The developed library provides four structural variations that are most popular in RFIC design; standard spiral structure, patterned ground shield(PGS) structure to enhance quality factor, stacked structure to enable high inductance values in a given silicon area, multilayer structure to lower series resistance. Electromagnetic simulation, equivalent circuit, and parameter extraction processes have been verified based on measurement results. The extensive measurement and simulation results of the inductor library can be a great asset for low cost RFIC design and development.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.632-635
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• 2008

In this paper, a diplexer circuit to separate GSM/CDMA band is designed using a LTCC (Low Temperature Cofired Ceramic) multi-layer technology. In order to increase a integration capability of the diplexer, it is designed in 6-layer LTCC sunstrate with a elative dielectric constant of 7.2 using 3-dimensional (3-D) multi-layer inductors and capacitors. The size of the designed diplexer including CB-CPW pads is $3,450{\times}4,000{\times}600{\mu}m^3$. An insertion loss (IL) and return loss of GSM band are less than -0.23dB and -10dB, respectively. In the case of CDMA band, the IL of -0.53dB and RL of below -10dB are archieved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1267-1271
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• 2009

In this paper, a diplexer circuit to separate GSM from CDMA band is designed using a LTCC (Low Temperature Cofired Ceramic) multi-layer technology. In order to increase a integration capability of the diplexer, it is designed using 3-dimensional (3-D) multi-layer compact inductor and capacitors in e-layer LTCC substrate with a relative dielectric constant of 7. In order to achieve high selectivity of the bands, a shunt capacitor and inductor are designed in the high-pass filter (HPF) and low-pass filter (LPF), respectively. The size of the fabricated diplexer including CPW pads is 3,450 ${\times}$4,000 ${\times}$694 ${\mu}m^3$An insertion loss (IL) and return loss in GSM band are less than -1.35dB and more than -5.66dB,respectively. In the case of CDMA band, the IL of -1.54dBandRLof above -9.30dBare archived.