• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.35-41
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• 2013

An efficient multi-stage rectifier for wireless power transfer in deep implant medical devices is implemented using $0.18-{\mu}m$ CMOS technology. The presented three-stage rectifier employs a cross-coupled topology to boost a small input AC signal from the external device to produce a 1.2-1.5 V output DC signal for the implant device. The designed rectifier achieves a maximum measured power conversion efficiency of 70% at 13.56 MHz under the conditions of a low 0.6-Vpp RF input signal with a $10-k{\Omega}$ output load resistance.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1581-1583
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• 2002

본 논문은 다공질 실리콘 다이어프램에 대한 화학 센서의 일종인 습도, 에탄올, 메탄올의 감지 특성을 측정하고 전기 전도도의 변화를 고찰하였다. 먼저, TMAH 용액으로 실리콘 다이어프램을 제작한 후, HF와 에탄올의 혼합 용액내에서 일정 전압을 인가하여 다공질 실리콘 다이어프램을 형성하였다. 다공질 실리콘을 면(100)에 수직한 방향으로 $50{\sim}100{\mu}m$ 두께로 균일하게 형성하여 p+-PSi-n+ 구조의 소자를 제작하였다. 다공질 실리콘 다이어프램의 절대습도에 대한 감도는 입력 주파수 5kHz에서 인가 전압이 $2{\sim}6$Vpp에서 $376.3{\sim}784.8{\Omega}$/%RH으로 변하였다. 또, 인가 전압 6Vpp에서 입력 주파수가 $2{\sim}5$kHz으로 변할 때 $393.3{\sim}784.8{\Omega}$/%RH으로 변하였다. 또한, 에탄올에 대한 감도는 $0.068{\mu}A$/%이며, 메탄올은 $0.212{\mu}A$/%으로 다공질 실리콘 다이어프램은 에탄올 보다 메탄올이 더 민감하게 반응하였다. 일반적으로 다공질 실리콘의 전기전도도는 charged surface traps과 screening effect에 의존한다.

• Journal of Aerospace System Engineering
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• v.11 no.6
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• pp.56-63
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• 2017

Thrust force induced by the dielectric barrier discharge inside of cylinder pipes is measured for various conditions. The input peak-to-peak voltage and frequency are varied from 2 to 9 kVpp and from 5 to 15 kHz, respectively. The height of cylinder is varied from 50 to 100 mm. The results of the measurements show that the magnitude of the generated thrusts increases as the voltage and the frequencies increase. It also shows that the generated thrusts are decreased according to the increase in the height of the cylinder. The cause of the thrust decrease is discussed in terms of energy losses due to the frictions on the wall surface.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.143-146
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• 2011

A 50-MS/s 10-bit pipelined ADC with 1.2Vpp differential input range is proposed in this paper. The designed pipelined ADC consists of eight stage of 1.5bit/stage, one stage of 2bit/stage, digital error correction block, bias & reference driver, and clock generator. 1.5bit/stage is consists of sub-ADC, DAC and gain stage, Specially, a sample-and hold amplifier (SHA) is removed in the designed pipelined ADC to reduce the hardware and power consumption. Also, the proposed bootstrapped switch improves the Linearity of the input analog switch and the dynamic performance of the total ADC. The reference voltage was driven by using the on-chip reference driver without external reference. The proposed pipelined ADC was designed by using a 0.18um 1-poly 5-metal CMOS process with 1.8V supply. The total area including the power decoupling capacitor and power consumption are $0.95mm^2$ and 60mW, respectively. Also, the simulation result shows the ENOB of 9.3-bit at the Nyquist sampling rate.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1227-1234
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• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

• Journal of Integrative Natural Science
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• v.5 no.4
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• pp.237-240
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• 2012

In this study, PEDOT thin films polymerized with Iron(III)tosylate ($Fe(PTS)_3$) and grown on atomically smooth and highly dense 3-aminopropyltriethoxysilane self-assembled monolayer (APS-SAM) surfaces by VPP method have been investigated. PEDOT thin films were synthesized on APS self-assembled $SiO_2$ wafer surface at two different concentrations (20 wt% and 40 wt%) and growth time (3 and 30 minutes), and then their sheet resistance were measured and compared. PEDOT thin films grown with 20 wt% $Fe(PTS)_3$ oxidant are highly conductive when compared with the film grown with 40 wt% $Fe(PTS)_3$, as ascertained by the measured sheet resistance values down to 0.06 ${\Omega}/cm$. It clearly suggests that 20 wt% is more effective oxidant concentration for VPP than 40 wt% even though the film grown with 40 wt% oxidant has better quality than the film with 20 wt% $Fe(PTS)_3$ does.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.59-67
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• 2007

This paper presents a low power dual-level low voltage differential signaling (DLVDS) technique using current source switching for LCD driver ICs in portable products. The transmitter makes dual level signal that has two different level signal 400mVpp and 250mVpp while keeping the advantages of LVDS. The decoding circuit recovers the primary signal from DLVDS. The low power DLVDS is implemented using a $0.25{\mu}m$ CMOS process under 2.5V supply. The proposed circuit shows 800Mbps/2-line data rate and 9mW, 11.5mW power consumptions in transmitter and receiver, respectively. The proposed DLVDS scheme reduce power consumption dramatically compare with conventional one.

• Journal of IKEEE
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• v.28 no.1
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• pp.78-89
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• 2024

PMIC chips based on a BCD process used in automotive semiconductors require multi-time programmable (MTP) intellectual property (IP) that does not require additional masks to trim analog circuits. In this paper, MTP cell size was reduced by about 18.4% by using MTP cells using PMOS capacitors (PCAPs) instead of NMOS capacitors (NCAPs) in MTP cells, which are single poly EEPROM cells with two transistors and one MOS capacitor for small-area MTP IP design. In addition, from the perspective of MTP IP circuit design, the two-stage voltage shifter circuit is applied to the CG drive circuit and TG drive circuit of MTP IP design, and in order to reduce the area of the DC-DC converter circuit, the VPP (=7.75V), VNN (=-7.75V) and VNNL (=-2.5V) charge pump circuits using the charge pumping method are placed separately for each charge pump.

• Journal of the East Asian Society of Dietary Life
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• v.18 no.6
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• pp.918-926
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• 2008

It is well known non-drug therapy for hypertension patients can reduce blood pressure. These types of therapy include maintaining ones ideal body weight, quitting smoking, consuming large amounts of fruits and vegetables consuming low levels of saturated fat and salt and regular exercise. Fermented milk protein derived biologically active peptides such as isoleucine-proline-proline_(IPP) or valine-proline-proline_(VPP) have been shown to lower blood pressure in hypertensive subjects. This study was conducted to investigate the antihypertensive effects of medical nutritional therapy _(MNT) in accordance with the consumption of fermented milk enriched with IPP and VPP. To accomplish this, we conducted a randomized case-controlled study of 43 subjects who had blood pressure levels greater than 120/80 mmHg. The subjects in the study group were randomly allocated into two groups, an MNT + fermented milk (100mL/day) group (n=21) and an MNT+L. helveticus fermented milk with tripeptides (IPP=2.2mg, VPP=2.6mg/100mL) group (n=22). The MNT included weight management, reduction of sodium, total fat and saturated fat intake, increased intake of fruits and vegetables, and increased intake of low fat dairy products. The treatments were administered for 12 weeks during which time no drug interventions were conducted. The daily intakes of total calories, fats, cholesterol and Na decreased significantly after 12 weeks of MNT in the control and the experimental groups. In addition, the systolic blood pressure de creased significantly in the control and experimental groups; however, the diastolic blood pressure only decreased significantly in the experimental group. Overall, the results of this study indicate that the intake of fermented milk containing IPP and VPP in conjunction with MNT exerted positive effects on the blood pressure of pre- and hypertensive subjects.