• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.371-380
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• 2006

This paper utilizing model picture of finished clothes in fashion design field various material (textile fabrics) doing Draping directly can invent new design, and do not produce direction sample or poetic theme width and confirm clothes work to simulation. Also, construct database about model and material image and embodied system that can confirm Mapping result by real time. And propose clothes simulation system to dress to 3D human body model of imagination because using several cloth pieces first by process to do so that can do simulation dressing abstracted poetic theme width to 3D model here. Proposed system creates 3D model who put clothes by physical simulation that do fetters to mass-spring model after read 3D human body model file and 2D foundation pattern file. System of this treatise examines collision between triangle that compose human body model for realistic simulation and triangle that compose clothes and achieved reaction processing. Because number of triangle to compose human body is very much, this collision examination and reaction processing need much times. To solve this problem, treatise that see could create realistic picture by method to diminish collision public prosecutor and reaction processing number, and could dress clothes to imagination human body model within water plant taking advantage of Octree space sharing techniques.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.