• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.6
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• pp.409-413
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• 2012

In this study, a substrate-bias assisted 2-step pulse programming method is proposed for realizing 4-bit/1-cell operation of the SONOS memory. The programming voltage and time are considerably reduced by this programming method than a gate-bias assisted 2-step pulse programming method and CHEI method. It is confirmed that the difference of 4-states in the threshold voltage is maintained to more than 0.5 V at least for 10-year for the multi-level characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.258-258
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• 2010

In this work, back bias effects in the program of the silicon-oxide-nitride-oxide-silicon (SONOS) cell using two-step pulse sequence, are investigated. Two-step pulse sequence is composed of the forward biases for collecting the electrons at the substrate terminal and back bias for injecting the hot electrons into the nitride layer. With an aid of the back bias for electron injection, we obtain a program time as short as 600 ns and an ultra low-voltage operation with a substrate voltage of -3 V.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.219-225
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• 2013

Program and erase characteristics of the elliptic gate all around (e-GAA) SONOS cell have been studied as the variation of eccentricity of the channel. An analytic program and erase model for the elliptic GAA SONOS cell is proposed and evaluated. The model shows that the ISPP (incremental-step-pulse programming) property is changed non-linearly as the eccentricity of the e-GAA SONOS cell is increased. It is differently from the well known linear relationship for that of 2D SONOS and even 3D circular SONOS cell with program bias. We can find that the simulation results of ISPP characteristics are in accord with the experimental data.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.2
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• pp.125-131
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• 2001

When the program voltage is applied to a word line, a part of the boosted channel charge in inhibited bit lines is lost due to the coupling between the string select line (SSL) and the adjacent word line. This phenomenon causes the program disturbance in the cells connected to the inhibited bit lines. This program disturbance becomes more serious, as the word line pitch is decreased. To reduce the word line coupling, the rising edge of the word-line voltage waveform was changed from a pulse step into a ramp waveform with a controlled slope. The word-line ramping circuit was composed of a timer, a decoder, a 8 b D/A converter, a comparator, and a high voltage switch pump (HVSP). The ramping voltage was generated by using a stepping waveform. The rising time and the stepping number of the word-line voltage for programming were set to $\mutextrm{m}-$ and 8, respectively,. The ramping circuit was used in a 512Mb NAND flash memory fabricated with a $0.15-\mutextrm{m}$ CMOS technology, reducing the SSL coupling voltage from 1.4V into a value below 0.4V.