• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.9-16
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• 2008

This paper presents a new Boolean extraction technique for logic synthesis. This method extracts two-cube Boolean subexpression pairs from each logic expression. It begins by creating two-cube array, which is extended and compressed with complements of two-cube Boolean subexpressions. Next, the compressed two-cube array is analyzed to extract common subexpressions for several logic expressions. The method is greedy and extracts the best common subexpression. Experimental results show the improvements in the literal counts over well-known logic synthesis tools for some benchmark circuits.

• Journal of the Korea Computer Industry Society
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• v.8 no.4
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• pp.229-236
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• 2007

A factored form is a sum of products of sums of products, ..., of arbitrary depth. Factoring is the process of deriving a parenthesized form with the smallest number of literals from a two-level form of a logic expression. The factored form is not unique and described as either algebraic or Boolean. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube Boolean subexpressions from given two-level logic expression and to extract divisor/quotient pairs. Then, we derive extended divisor/quotient pairs, where their quotients are not cube-free, from the generated divisor/quotients pairs. We generate quotient/quotient pairs from divisor/quotient pairs and extended divisor/quotient pairs. Using the pairs, we make a matrix to generate Boolean factored form based on a technique of rectangle covering.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.11
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• pp.4597-4603
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• 2010

A factorization is a very important part of multi-level logic synthesis. The number of literals in a factored form is an estimate of the complexity of a logic function, and can be translated directly into the number of transistors required for implementation. Factored forms are described as either algebraic or Boolean, according to the trade-off between run-time and optimization. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube nonkernel Boolean pairs from given expression. Experimental results on various benchmark circuits show the improvements in literal counts over previous other factorization methods.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.8
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• pp.3715-3722
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• 2011

This paper presents a new Boolean extraction technique for logic synthesis. This method first calculates divisor/2-cube quotients, 2-cube quotient pairs, and 2-cube quotient matrices. Then we find candidates, which can be common sub-expressions, from 2-cube quotients and matrices. Next, candidate intersection provides the common sub-expressions for several logic expressions. Experimental results show the improvements in literal counts over the previous methods.

• Journal of the Korea Computer Industry Society
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• v.7 no.4
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• pp.293-298
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• 2006

A factorization is an extremely important part of multi-level logic synthesis. The number of literals in a factored form is a good estimate of the complexity of a logic function, and can be translated directly into the number of transistors required for implementation. Factored forms are described as either algebraic or Boolean, according to the trade-off between run-time and optimization. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube Boolean subexpression pairs from given expression. Experimental results on various benchmark circuits show the improvements in literal counts over the algebraic factorization based on Bryton's co-kernel cube matrix.

• Journal of the Korea Computer Industry Society
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• v.7 no.5
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• pp.473-480
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• 2006

Extraction is tile most important step in global minimization. Its approache is to identify and extract subexpressions, which are multiple-cubes or single-cubes, common to two or more expressions which can be used to reduce the total number of literals in a Boolean network. Extraction is described as either algebraic or Boolean according to the trade-off between run-time and optimization. Boolean extraction is capable of providing better results, but difficulty in finding common Boolean divisors arises. In this paper, we present a new method for Boolean extraction to remove the difficulty. The key idea is to identify and extract two-cube Boolean subexpression pairs from each expression in a Boolean network. Experimental results show the improvements in the literal counts over the extraction in SIS for some benchmark circuits.