• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.211-214
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• 2000

In this paper, a discrete-time S-dimensional chaos circuit (S = 1,2,3,4,...) with array structure is proposed. By employing array structure which consists of 1-dimensional chaos circuits, the proposed circuit can achieve long working-life. This feature is favorable to exploit as a building block of chaos application systems to get into home electric appliances. Further more, the proposed circuit synthesized using switched-current (SI) techniques is suitable for integration. Concerning the proposed circuit, SPICE simulations are performed. SPICE simulations showed that the proposed circuit can generate the chaotic signals in spite of the fault of the building blocks of the proposed circuit. The proposed circuit is integrable by a standard BiCMOS technology.

• 대한전자공학회논문지
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• 제25권9호
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• 한국방재학회 논문집
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• 제5권2호
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• pp.1-8
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• 2005

콘크리트 구조물 내부 결함이나 철근 위치를 탐지하기 위하여 초단파를 이용하는 비파괴 시험방법이 구조물 안전진단 분야에서도 최근 관심을 불러일으키고 있다. 본 연구의 목적은 기 개발된 2차원 영상화 방법을 확장하여 3차원 영상처리방법을 개발하는 것이다. 그 방법으로 콘크리트 구조물 내의 결함을 탐지하기 위한 안테나를 구성, 수치적 초점조절시스템을 이용하여 송신부와 수신부의 초점을 동시 조절하여 구조물 내부의 모든 부분을 검색하였다. 또한 다중주파수 방식을 이용, 데이터의 오류를 제거하고 해상도를 향상시켜 구조물 내부의 결함이나 내부모습을 탐지할 수 있는 3차원 영상장치를 개발하고자 하였다. 실험 결과, 데이터 오류를 줄이는 다중주파수방식에 의하여 재현된 영상의 정확성을 검증하고, 주파수 조절방법에 의하여 $4{\times}4$ 안테나배열을 설계함으로써 5.2 GHz에서 주파수대역의 우수한 투과성능을 입증하였다. 즉 본 연구에서 개발된 슬롯안테나는 파동의 방사기능과 주파수대역의 넓이 등에서 구조부재의 결함탐지에 이용될 수 있음을 검증하였다.

• 한국전자통신학회논문지
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• 제13권2호
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• pp.411-418
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• 2018

본 논문에서는 집적영상에서 가상광학과 혼돈 수열(chaos sequence)을 결합하여 3차원 물체 영상을 암호화는 새로운 방법을 제안한다. 먼저 가상 핀홀 배열(virtual pinhole array)을 통하여 2차원 요소영상 배열(EIA)을 생성한 후, 이를 이용해 3차원 물체를 디지털로 만든다. 그 후 혼돈 수열의 논리적 연산을 통해 최종 암호화 영상을 만든다. 이러한 방법은 영상 데이터를 시각화하기 위한 영상의 기본 정보인 픽셀의 값을 변환시키기 때문에 기존의 암호화 방법보다 향상된 암호화 결과를 얻을 수 있다. 실험을 통해 본 암호화 방법의 유효성과 안정성을 검증한다.

• Food Science and Biotechnology
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• 제14권4호
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• pp.554-557
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• 2005

As a device for taste sensation, an 8-channel taste evaluation system was prepared and applied for discriminant analysis of marketed liquor. The biomimetic polymer membranes for the system were prepared through a casting procedure by employing polyvinyl chloride, bis (2-ethylhexyl)sebacate as plasticizer and electroactive materials such as valinomycin in the ratio of 33:66:1, and were separately attached over the sensitive area of ion-selective electrodes to construct the corresponding taste sensor array. The sensor array in conjunction with a double junction reference electrode was connected to a high-input impedance amplifier and the amplified sensor signals were interfaced to a personal computer via an A/D converter. When the signal data from the sensor array for 3 groups of marketed liquor like Maesilju, Soju and beer were analyzed by principal component analysis after normalization, it was observed that the 1st, 2nd and 3rd principal component were responsible for most of the total data variance, and the analyzed liquor samples were discriminated well in 2 dimensional principal component planes composed of the 1st-2nd and the 1st-3rd principal component.

• 한국음향학회지
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• 제20권2호
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• pp.86-92
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• 2001

소음원 위치와 방위를 규명하기 위해 다양한 배열처리기술이 발전되어 왔다. 배열처리기술의 기본은 두 개의 수신센서에 수신된 신호의 시간차를 이용하여 소음원의 위치와 방위를 구하는 것으로 응용분야나 신호처리방법에 따라 고유의 특성을 갖는 빔형성기법, 상관함수기법 및 NAH (Near-Field Acoustic Holography) 등이 있다 본 연구에서는 이러한 기법들 중 광대역 소음원 탐지에 적용되는 상관함수기법을 채택하여 소음원의 대역폭과 측정 잡음원 간의 상관 관계가 위치나 방위 탐지 정확도에 미치는 영향을 분석하여 효과적인 소음원 탐지기법을 제안한다. 본 연구에서 채택한 배열의 기하학적 형상은 위치나 방위의 3차원적 모호성을 없애기 위한 3차원 비선형이며 제안된 기법의 타당성은 수치모의 실험 및 실제 실험으로 검증되었다.

• 한국세라믹학회지
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• 제55권2호
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• pp.108-115
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• 2018

The increasing demands for three-dimensional (3D) electronic and optoelectronic devices have triggered interest in epitaxial growth of 3D semiconductor materials. However, most of the epitaxially-grown nano- and micro-structures available so far are limited to certain forms of crystal arrays, and the level of control is still very low. In this review, we describe our latest progress in 3D epitaxy of oxide and nitride semiconductor crystals. This paper covers issues ranging from (i) low-temperature solution-phase synthesis of a well-regulated array of ZnO single crystals to (ii) systematic control of the axial and lateral growth rate correlated to the diameter and interspacing of nanocrystals, as well as the concentration of additional ion additives. In addition, the critical aspects in the heteroepitaxial growth of GaN and InGaN multilayers on these ZnO nanocrystal templates are discussed to address its application to a 3D light emitting diode array.

• 한국전자파학회논문지
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• 제26권8호
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• pp.758-764
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• 2015

본 논문에서는 2차 함수 곡선의 회전체형 도체 곡면 위에 있는 컨포멀 배열 안테나의 패턴을 EAGA(Enhanced Adaptive Genetic Algorithm)를 이용하여 합성한 내용을 보이고 있다. 다양한 곡면의 회전체 도체를 고찰하기 위해 2차 함수의 계수를 바꿔 세 가지 유형의 회전체형 곡면을 형성시켰고, 각 유형의 컨포멀 배열 안테나 패턴을 합성하였다. 패턴 합성에 소요되는 시간의 단축을 위해 3차원 컨포멀 배열 안테나의 능동 소자 패턴 대신에 2차원 평면 배열 안테나의 능동 소자 패턴을 구한 후, 이를 오일러 변환(Euler transform)시켜 이용하였다. EAGA를 이용하여 합성된 패턴의 검증을 위해 MWS(Microwave Studio)를 통해 구한 패턴과 비교하였으며, 두 패턴은 전반적으로 유사하였다.

• 전기학회논문지
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• 제64권12호
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• pp.1730-1736
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• 2015

This paper presents a 16-channel transimpedance amplifier (TIA) array implemented in a standard $0.18-{\mu}m$ CMOS technology for the applications of panoramic scan LADAR (PSL) systems. Since this array is the front-end circuits of the PSL systems to recover three dimensional image for unmanned vehicles, low-noise and high-gain characteristics are necessary. Thus, we propose a voltage-mode inverter TIA (I-TIA) array in this paper, of which measured results demonstrate that each channel of the array achieves $82-dB{\Omega}$ transimpedance gain, 565-MHz bandwidth for 0.5-pF photodiode capacitance, 6.7-pA/sqrt(Hz) noise current spectral density, and 33.8-mW power dissipation from a single 1.8-V supply. The measured eye-diagrams of the array confirm wide and clear eye-openings up to 1.3-Gb/s operations. Also, the optical pulse measurements estimate that the proposed 16-channel TIA array chip can detect signals within 20 meters away from the laser source. The whole chip occupies the area of $5.0{\times}1.1mm^2$ including I/O pads. For comparison, a current-mode 16-channel TIA array is also realized in the same $0.18-{\mu}m$ CMOS technology, which exploits regulated-cascode (RGC) input configuration. Measurements reveal that the I-TIA array achieves superior performance in optical pulse measurements.

• Journal of Information Display
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• 제13권2호
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• pp.55-59
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• 2012

In this paper, a concept of an integrated elastomer substrate for a three-dimensional (3D) liquid crystal display based on the integral-imaging method is presented. The elemental lens array and columnar spacers were integrated into one of the two substrates, an elastomer substrate, through an imprinting process. The integrated elastomer substrate was capable of maintaining the uniform liquid crystal (LC) cell gap and promoting homeotropic LC alignment without any surface treatment. The monolithic approach reported herein will provide a key component for 3D displays with enhanced portability through a more than 40% weight reduction compared with the conventional integral-imaging method.