• Title/Summary/Keyword: 1000 Ethernet

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Security of Ethernet in Automotive Electric/Electronic Architectures (차량 전자/전기 아키텍쳐에 이더넷 적용을 위한 보안 기술에 대한 연구)

  • Lee, Ho-Yong;Lee, Dong-Hoon
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.16 no.5
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    • pp.39-48
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    • 2016
  • One of the major trends of automotive networking architecture is the introduction of automotive Ethernet. Ethernet is already used in single automotive applications (e.g. to connect high-data-rate sources as video cameras), it is expected that the ongoing standardization at IEEE (IEEE802.3bw - 100BASE-T1, respectively IEEE P802.3bp - 1000BASE-T1) will lead to a much broader adoption in future. Those applications will not be limited to simple point-to-point connections, but may affect Electric/Electronic(EE) Architectures as a whole. It is agreed that IP based traffic via Ethernet could be secured by application of well-established IP security protocols (e.g., IPSec, TLS) combined with additional components like, e.g., automotive firewall or IDS. In the case of safety and real-time related applications on resource constraint devices, the IP based communication is not the favorite option to be used with complicated and performance demanding TLS or IPSec. Those applications will be foreseeable incorporate Layer-2 based communication protocols as, e.g., currently standardized at IEEE[13]. The present paper reflects the state-of-the-art communication concepts with respect to security and identifies architectural challenges and potential solutions for future Ethernet Switch-based EE-Architectures. It also gives an overview and provide insights into the ongoing security relevant standardization activities concerning automotive Ethernet. Furthermore, the properties of non-automotive Ethernet security mechanisms as, e.g., IEEE 802.1AE aka. MACsec or 802.1X Port-based Network Access Control, will be evaluated and the applicability for automotive applications will be assessed.

Optical transceiver Design Using Optical Multiplexing Method of Ethernet Base (Ethernet 기반의 광다중화 방식을 이용한 광 송수신기 설계)

  • 염진수;임재산;이영우;허창우
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.7
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    • pp.1569-1574
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    • 2003
  • 최근에 VOD, HDTV, 라이브 스트리밍 등의 서비스가 늘어나면서 가입자들은 광대역 서비스를 요구하고 있다. 이를 가입자에게 제공하기 위해서는 광대역폭을 지원할 수 있는 FTTH(Fiber to The Home)의 실현이 필수적이며, FTTH의 고비용과 설비 문제를 해결하기 위한 대안으로 PON(Passive Optical Network)이 부상하고 있다. PON은 네트워크를 시스템이 아닌 소자로 구성해, 일정거리까지는 하나의 광 회선을 설치하고 스플리터를 중심으로 여러 개로 회선을 분배하는 것이다. 이 또한 스플리터의 한계로 분배할 수 있는 회선이 제한적이며, 이를 해결하기 위한 방법으로 WDM(Wavelength Division Multiplexing)-PON이 고려되고 있다. 이에 본 논문에서는 WDM-PON에 적용할 수 있는 Ethemet 기반의 광 송수신 채널 유닛을 설계하였다. 채널 유닛은 1000BASE-T Ethernet 신호를 입력받아 파장별 DFB-LD에 직접 변조하는 방식을 사용하여 구현하였다

Design and Verification of PCS Transmitting and Receiving Module for 40/100 Gigabit-Ethernet (40G/100G 이더넷을 위한 PCS 송수신부 설계 및 기능 검증)

  • Han, Kyeong-Eun;Kim, Seung-Hwan;Ahn, Kye-Hyun;Kim, Kwang-Joon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.11B
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    • pp.1579-1587
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    • 2010
  • In this paper, we design the PCS(Physical Coding Sublayer) transmitting and receiving module for 400/1000 Ethernet and verify the performance of it through logic simulation. In this work, we defined each function module and internal/external control signals and implemented them using HDL programming language. We also designed 64B/66B encoding/decoding, scrambling/descrambling including operation mode, detection of invalid frames, and multi-lane based distribution/arrangement. It was simulated using ModelSim and verified in terms of the operation and timing according to input data. The simulation result shows that all designed modules in 400/100G Ethernet are correctly performed.

A Design and Implementation of OTU4 Framer for l00G Ethernet (100G 이더넷 수용을 위한 OTU4 프레이머 표준기술 설계 및 구현)

  • Youn, Ji-Wook;Kim, Jong-Ho;Shin, Jong-Yoon;Kim, Kwang-Joon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.12B
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    • pp.1601-1610
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    • 2011
  • This paper discusses standardization activities, requirements and enabling technologies for 100G Ethernet and 100G OTN. The need of 100Gbps transport capacity has been gaining greater interest from service providers and carrier vendors. Moreover, optical transport networks based on OTN/DWDM are changing their properties to apply Ethernet traffic which is dramatically increasing. We realize and experimentally demonstrate OTU4 framer with commercial FPGA. The key features of the realized OTU4 framer are parallel signal processing function, multi-lane distribution function, GMP function and FEC function. The realized OTU4 framer has the large signal processing capacity of 120Gbps, which allows to transport about 120Gbps client signals such as $12{\times}10G$ Ethernet and $3{\times}40G$ Ethernet. The realized OTU4 framer has the advantages to quickly adjust to changing markets and new technologies by using commercial FPGA instead of ASIC.

Implementation of a Viterbi Decoder Operated in the 1000Base-T (1000Base-T에서 동작하는 Viterbi Decoder 구현)

  • Jung, Jae-woo;Chung, Hae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.41-44
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    • 2013
  • As appearance of high-quality service such as UDTV application, high-speed and high-capacity communication services are required. For this, communication systems increase the data processing speed and use various error correction techniques. In this paper, we implement the Viterbi decoder applied in 1000BASE-T with 4 pairs UTP cable. The minimum operating speed of the Viterbi decoer should be more than 125 MHz because 125 MHz PAM-5 signal is transmitted on each pair of cables in 1000BASE-T. To do this, we implement the decoder by using the pipeline and parallel processing and verify the operation with 125 MHz by using a logic analyzer. Finally, we will show that the decoder recovers the original data for the added random error data.

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EPGA Implementation and Verification of CSIX Module (CSIX 모듈의 FPGA 구현 및 검증)

  • 김형준;손승일;강민구
    • Journal of Internet Computing and Services
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    • v.3 no.5
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    • pp.9-17
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    • 2002
  • CSIX-L1 is the Common Switch Interface that defines a physical interface for transferring information between a traffic manager (Network Processor) and a switching fabric in ATM, IP, MPLS, Ethernet and data communication areas. In Tx, data to be transmitted is generated in Cframe which is the base information unit and in Rx, original data is extracted from the received Cframe. CSIX-L1 suppots the 32, 64, 96, and 123-bit interface and generates a variable length CFrame and Idle Cframe. Also CSIX-L1 appends Padding byte and supports 16-bit Vertical parity, CSIX-L1 is designed using Xilinx 4,1i. After functional and timing simulations are completed. CSIX-L1 module is downloaded in Xilinx FPGA XCV1000EHQ240C and verified. The synthesized CSIX module operates at 27MHz.

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An Implementation of 16-channel DSP System with Ethernet/USB Interface for Acquisition and Analysis (Ethernet/USB 기반 16채널 데이터 수집 및 분석 시스템 구현)

  • 유재현;송형훈;신현경;조성호
    • Proceedings of the IEEK Conference
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    • 2000.09a
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    • pp.505-508
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    • 2000
  • 본 논문에서는 16채널 혹은 8채널의 센서를 통해 들어오는 저주파대역의 아날로그 신호를 수집하고. 수집된 데이터를 실시간으로 처리하기 위한 고속의 신호처리 기능이 결합된 통합 DSP (Digital Signal Processor)시스템을 구현하였다. 구현된 시스템은 휴대가 용이하도록 소형으로 설계되어 있으며 노트북 등의 이동형 장비에 활용되도록 USB 인터페이스를 채택하였으며, 장치간의 네트워크 구성이 가능하도록 Ethernet 인터페이스를 추가하였다 Digital Signal Processor는 Texas Instrument 사의 TMS320C6701 부동소수점 연산방식의 고성능 DSP를 사용하여 16채널의 실시간 신호 분석이 가능하게 하였으며, ICP 센서 구동용 전류 공급부를 내장하여 센서 선택의 폭을 넓히었고, programmable gain amplifier인 PGA202증폭기를 사용하여 입력신호가 작을 경우 최대 1000배, 즉 60dB까지 입력신호를 증폭하여 수집 및 분석할 수 있다. 200kSPS의 샘플링 레이트와 16bit resolution을 가지는 AD976 A/D converter를 사용하여 채널당 0~6kHz의 신호대역폭을 가지며,differential 입력시 8 채널,single ended 입력시 16 채널의 입력 신호의 수집 및 분석이 가능하다. Windows 응용프로그램에서는 사용자가 원하는 입력신호 및 스펙트럼 실시간 분석, 입력신호 기록 및 저장, RPM 측정 및 분석, 외부 트리거 및 레벨 트리거를 이용한 입력신호 제어와 수집된 데이터를 바탕으로 원하는 제어가 가능한 응용프로그램 제작에 활용될 라이브러리가 포함된다.

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Optical transceiver Channel Unit design and implementation for WDM-PON system (WDM-PON 시스템 광 송수신 채널 유닛 설계 및 구현)

  • 염진수;임재산;이영우;허창우
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2003.10a
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    • pp.446-449
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    • 2003
  • 최근에 VOD, HDTV, 라이브 스트리밍 등의 서비스가 늘어나면서 가입자들은 광대역 서비스를 요구하고 있다. 이를 가입자에게 제공하기 위해서는 광대역폭을 지원할 수 있는 FITH(Fiber to The Home)의 실현이 필수적이며, FTTH의 고비용과 설비 문제를 해결하기 위한 대안으로 PON(Passive Optical Network)이 부상하고 있다. PON은 네트워크를 시스템이 아닌 소자로 구성해, 일정거리까지는 하나의 광 회선을 설치하고 스플리터를 중심으로 여러 개로 회선을 분배하는 것이다. 이 또한 스플리터의 한계로 분배할 수 있는 회선이 제한적이며, 이를 해결하기 위한 방법으로 WDM(Wave-length Division Multiplexing)-PON이 고려되고 있다. 이에 본 논문에서는 WDM-PON에 적용할 수 있는 Ethernet 기반의 광 송수신 채널 유닛을 설계하였다. 채널 유닛은 1000BASE-T Ethernet 신호를 입력받아 파장별 DFB-LD에 직접 변조하는 방식을 사용하여 구현하였다.

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Implementation of a Viterbi decoder operated in 4 Dimensional PAM-5 Signal of 1000Base-T (1000BASE-T의 4조 PAM-5 신호 상에서 동작하는 비터비 디코더의 구현)

  • Jung, Jae-Woo;Chung, Hae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.7
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    • pp.1579-1588
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    • 2014
  • The LAN method is the most widely used in domestic high-speed internet access and rapidly moving to 1 Gbps Ethernet from 100 Mbps one to provide high-speed services such as UHD TV. The 1000BASE-T PHY with 4 pairs UTP transmits a PAM-5 signal at the 125 MHz clock per each pair to achieve 1 Gbps rate. In order to correct errors over the channel, the transmitter uses a TCM which is combined the convolutional encoder and PAM-5, and the receiver uses the Viterbi decoder. In this paper, we implement a Viterbi decoder which can correct two pair errors and operate at the least 125 MHz clock speed. Finally, we will verify the error correction function and the operating speed of the implemented decoder with a logic analyzer.

A Study on Energy Savings in a Network Interface Card Based on Optimization of Interrupt Coalescing (인터럽트 병합 최적화를 통한 네트워크 장치 에너지 절감 방법 연구)

  • Lee, Jaeyoul;Han, Jaeil;Kim, Young Man
    • Journal of Information Technology Services
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    • v.14 no.3
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    • pp.183-196
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    • 2015
  • The concept of energy-efficient networking has begun to spread in the past few years, gaining increasing popularity. A common opinion among networking researchers is that the sole introduction of low consumption silicon technologies may not be enough to effectively curb energy requirements. Thus, for disruptively boosting the network energy efficiency, these hardware enhancements must be integrated with ad-hoc mechanisms that explicitly manage energy saving, by exploiting network-specific features. The IEEE 802.3az Energy Efficient Ethernet (EEE) standard is one of such efforts. EEE introduces a low power mode for the most common Ethernet physical layer standards and is expected to provide large energy savings. However, it has been shown that EEE may not achieve good energy efficiency because mode transition overheads can be significant, leading to almost full energy consumption even at low utilization levels. Coalescing techniques such as packet coalescing and interrupt coalescing were proposed to improve energy efficiency of EEE, but their implementations typically adopt a simple policy that employs a few fixed values for coalescing parameters, thus it is difficult to achieve optimal energy efficiency. The paper proposes adaptive interrupt coalescing (AIC) that adopts an optimal policy that could not only improve energy efficiency but support performance. AIC has been implemented at the sender side with the Intel 82579 network interface card (NIC) and e1000e Linux device driver. The experiments were performed at 100 M bps transfer rate and show that energy efficiency of AIC is improved in most cases despite performance consideration and in the best case can be improved up to 37% compared to that of conventional interrupt coalescing techniques.