• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.26 no.10
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• pp.491-496
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• 2014

In general, the entire air supply of a bio-safety laboratory (BSL) should be exhausted on the outside to ensure bio-safety, and the air conditioning system should always be operated to maintain a difference in the room pressure. As a result, the annual energy consumption of such a building is approximately five or ten times higher than that of an office building of the same magnitude. Thus, this study applies an actual operating system that targets BSL. The energy consumption is analyzed using the Energy Plus V8.0 program (an energy analysis program), and five kinds of cases that depend on the energy consumption of the basic BSL system are also analyzed. As a result, the energy consumption in Case 1 (basic system) is of 324.95 GJ. When the basic system of Case 1 is compared to that in Case 2 (basic system+passive design with exterior envelopes), an annual energy savings of is 6.9% is achieved. For Case 3 (basic system+Photovoltaic, PV) 12.7% is achieved, and for Case 4 (Solar Geothermal Hybrid System of renewable energy, SGHS) 49.5% is achieved. If a passive design with exterior envelopes and renewable energy system (PV+SGHS) is combined, as in Case 5, the energy consumption would be 118.15 GJ. Therefore, when this last system is compared to a basic system, the passive design with exterior envelopes and renewable energy system (PV+SGHS) can reduce energy consumption by 63.6%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.433-448
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• 2012

A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weight-adjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only $0.152mm^2$ and consumes 69.8 mW, while the rest of the receiver occupies $0.297mm^2$ and consumes 56.0 mW at the 7- Gb/s data-rate and supply voltage of 1.35 V.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.530-530
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• 2012

Many practical applications of carbon nanotubes(CNTs) have been proposed and there have been attempts to utilize CNT films as transparent electrodes for solar cells and displays. Our group has considered the use of the CNT film as a thin film heater (TFH) and proposed it for the first time and reported the thermal behavior of the TFH made of single walled CNTs. However, due to the relatively high electrical resistance of the CNT film, using the TFH in application areas requiring high heat flux has been a difficult problem. To overcome this obstacle, we adopted a 'branch electrodes' concept to increase the film conductance dramatically. If two branch electrodes are inserted into a TFH whose original electrical resistance is R, the total resistance will be reduced to R/9. Because of the increased aspect ratio, the resistance of each segmented TFH will be reduced to R/3. Furthermore, since they are connected in parallel, the total resistance reduces to R/9. This could be extended to n branch electrodes, and the total resistance of the film will be reduced to R/(n+1)2, if the resistance of electrodes are negligibly small. We fabricated the heaters with different number of branch electrodes. The number of branch electrodes of the fabricated heaters are 0, 2, 4, 8 and their electrical resistance are 101.4, 39.5, 20.0, $15.4{\Omega}$, respectively. We applied 20V to each heater and monitored the temperature variations. We could achieve high heating temperature even with low voltage supply. This technique could be applied to relevant industrial applications which need high power film heater.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.6
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• pp.63-69
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• 2008

Reconfigurable RF one-chip solutions have been researched with the objective of designing for smaller-sized and more economical RF transceiver and it can be applied to a vehicular wireless terminal. The proposed voltage-controlled oscillator satisfies the targeted frequency range ($4.2{\sim}5.4\;GHz$) and the frequency planning which correspond to the standards such as CDMA(IS-95), PCS, GSM850, EGSM, WCDMA, WLAN, Bluetooth, WiBro, S-DMB, DSRC, GPS, and DVB-H/DMB-H/L(L Band). In order to improve phase noise performance, PMOS is adopted in the cross-coupled pair, the tail current source and MOS varactor in this VCO and differential-typed switching is proposed in capacitor array. Based on the measurement results, a total power dissipation is $5.3{\sim}6.0\;mW$ at 1.8 V power supply voltage. The oscillator is tuned from 4.05 to 5.62 GHz; The tuning range is 33%. The phase noise is -117.16 dBc/Hz at 1 MHz offset frequency and the FOM (Figure Of Merit) is $-180.84{\sim}-180.5$.

• Journal of Korean Society of Environmental Engineers
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• v.29 no.7
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• pp.820-825
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• 2007

Earthworm casting was the natural fertilizer that contained high concentrations of nutrients such as nitrogen, phosphate and potassium and of over $10^8$ CFU/ml of microorganisms. Greater than 80% of feed was excreted through the fermentation by the intestinal enzyme, after worm had eaten feeds such as fallen leaves and rotten roots under the ground. Also, the soil structure of casting was known to be very efficient in the aspects of the porosity, the water permeability, and deodorizing activities. In this research, the biofilter packed with a biomedia made of casting and waste polyurethane foam, a binder, which helped to improve the durability and perpetuity of casting, was investigated to degrade malodorous hydrogen sulfide gas. The biomedia had no need of extra supply of nutrients and of microbial inoculations. On the beginning of the operations, it showed 100% removal of hydrogen sulfide gas without lag phase. At SV of 50 $h^{-1}$, hydrogen sulfide gas from the outlet of the biofilter was not detected, when inlet concentration increased to 450 ppmv. After that, removal efficiency decreased as increasing inlet hydrogen sulfide concentration. Hydrogen sulfide removal was maintained at almost 93% until inlet concentration was increased up to 950 ppmv, at which the elimination capacity of $H_2S$ was 61.2 g $S{\cdot}m^{-3}{\cdot}h^{-1}$. Maximum elimination capacity guaranteing 90% removal was 61.2, 65.9, 84.7, 89.4 g $S{\cdot}m^{-3}{\cdot}h^{-1}$ at SV ranging from 50 $h^{-1}$ to 300 $h^{-1}$, but was 59.3 g $S{\cdot}m^{-3}{\cdot}h^{-1}$ at SV of 400 $h^{-1}$. The results calculated from Michaelis-Menten equation revealed that $V_m$ increased from 66.04, 88.96, 117.35, 224.15, to 227.54 g $S{\cdot}m^{-3}{\cdot}h^{-1}$ with increasing space velocity in the range of 50 $h^{-1}$ to 400 $h^{-1}$. However, saturation constant$(K_s)$ decreased from 79.97 ppmv to 64.95 and 65.37 ppmv, and then increased to 127.72 and 157.43 ppmv.

• Journal of Ocean Engineering and Technology
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• v.37 no.2
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• pp.58-67
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• 2023

While extensive research is being conducted to reduce greenhouse gases in industrial fields, the International Maritime Organization (IMO) has implemented regulations to actively reduce CO₂ emissions from ships, such as energy efficiency design index (EEDI), energy efficiency existing ship index (EEXI), energy efficiency operational indicator (EEOI), and carbon intensity indicator (CII). These regulations play an important role for the design and operation of ships. However, the calculation of the index and indicator might be complex depending on the types and size of the ship. Here, to calculate the EEDI of two target vessels, first, the ships were set as Deadweight (DWT) 50K container and 300K very large crude-oil carrier (VLCC) considering the type and size of those ships along with the engine types and power. Equations and parameters from the marine pollution treaty (MARPOL) Annex VI, IMO marine environment protection committee (MEPC) resolution were used to estimate the EEDI and their changes. Technical measures were subsequently applied to satisfy the IMO regulations, such as reducing speed, energy saving devices (ESD), and onboard CO₂ capture system. Process simulation model using Aspen Plus v10 was developed for the onboard CO₂ capture system. The obtained results suggested that the fuel change from Marine diesel oil (MDO) to liquefied natural gas (LNG) was the most effective way to reduce EEDI, considering the limited supply of the alternative clean fuels. Decreasing ship speed was the next effective option to meet the regulation until Phase 4. In case of container, the attained EEDI while converting fuel from Diesel oil (DO) to LNG was reduced by 27.35%. With speed reduction, the EEDI was improved by 21.76% of the EEDI based on DO. Pertaining to VLCC, 27.31% and 22.10% improvements were observed, which were comparable to those for the container. However, for both vessels, additional measure is required to meet Phase 5, demanding the reduction of 70%. Therefore, onboard CO₂ capture system was designed for both KCS (Korea Research Institute of Ships & Ocean Engineering (KRISO) container ship) and KVLCC2 (KRISO VLCC) to meet the Phase 5 standard in the process simulation. The absorber column was designed with a diameter of 1.2-3.5 m and height of 11.3 m. The stripper column was 0.6-1.5 m in diameter and 8.8-9.6 m in height. The obtained results suggested that a combination of ESD, speed reduction, and fuel change was effective for reducing the EEDI; and onboard CO₂ capture system may be required for Phase 5.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.126-142
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• 2016

This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

• Korean Journal of Agricultural Science
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• v.21 no.2
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• pp.103-110
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• 1994

Since the supply of the Southeast Asian tropical timber decreases and its price steeply increases in the international lumber market, door and window frame manufacturers in this country are eagerly searching for their substitutes. This is the first step to replace Southeast Asian tropical timber by low grade North American softwoods, whose reliable and steady supply is expected, but their appearances are not as good as the tropical timber. In this study, knot distribution on the softwood boards and their warp were examined The yield and production cost were also calculated. The average numbers of knots on a door frame were 7.2 for Douglas-fir and 3.4 for Western hemlock. Only 11% of the knots of Douglas-fir door frames are larger than 5cm in diameter, while are 35% of the knots of Western hemlock. The deformations of door frames, after 2 months air-drying, were measured with a warp table. The deformations of Western hemlock door frames were mostly less than 6mm, while those of Douglas-fir distributed in the range of 0.5 and 9.5mm. The yield of Western hemlock is higher than that of Douglas-fir. It can be concluded that the door frames made of the softwoods are compatible with those made of the tropical timber in most aspects except appearance.