• 전자공학회논문지 IE
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• v.47 no.2
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• pp.13-20
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• 2010

This paper describes a current mode PWM DC-DC converter IC for battery charger and supply power converter for portable electronic devices. The maximum supply voltage of IC is 40[V] and 2.8[V]~330[V] DC input power is converted to higher or programmed DC voltage according to external resistor ratio or wire winding ratio of transformer. The maximum supply output current is 3[A] over and voltage error of output node is within 3[%]. The whole circuit needed current mode PWM DC-DC converter circuit is designed. The package dimensions and number of external parts are minimized in order to get a smaller hardware size. The power consumption is smaller then 1[mW] at stand by period with supply voltage of 3.6[V] and maximum energy conversion efficiency is about 86[%]. This device has been designed in a 0.6[um] double poly, double metal 40[V] CMOS process and whole chip size is 2100*2000 [um2].

• Nuclear Engineering and Technology
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• v.54 no.2
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• pp.661-665
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• 2022

The 3 MeV proton irradiation effects on SiGe low noise amplifier (LNA) (NXP BGU7005) performance under different voltage supply VCC (0 V, 2.5 V) conditions were firstly experimental studied in this present work. The S parameters including S₁₁, S₂₂, S₂₁, 1 dB compression point and noise figure (NF) of the test samples under different bias voltage supply were measured and compared before and after 3 MeV proton irradiation. The total proton irradiation fluence was 1 × 10¹⁵ protons/cm². The maximum degradation quantities of the gain S₂₁ and NF of the test samples under zero bias are measured respectively 1.6 dB and 1.2 dB. Compared with the samples under 2.5 V bias supply, the maximum degradation of S₂₁ and NF are respectively 1.1 dB and 0.8 dB in the whole frequency band. It is noteworthy that the gain and NF of SiGe LNAs under zero-bias mode suffer enhanced degradation compared with those under normal bias supply. The key influence factors are discussed based on the correlation of the SiGe device and the LNA circuit. Different process of the ionization damage and displacement damage under zero-bias and 2.5 V bias voltage supply contributed to the degradation difference. The underlying physical mechanisms are analyzed and investigated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.528-533
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• 2016

A low voltage high PSRR CMOS Bandgap circuit capable of generating a stable voltage of less than 1 V (0.8 V and 0.5 V) robust to Process, Voltage and Temperature (PVT) variations is proposed. The high PSRR of the circuit is guaranteed by a low-voltage current mode regulator at the central aspect of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage $V_{reg}$ for the BG core and Op-Amp rather than the VDD. These current mirrors reduce the impact of supply voltage variations. The proposed circuit is implemented in a $0.35{\mu}m$ CMOS technology. The BGR circuit occupies $0.024mm^2$ of the die area and consumes $200{\mu}W$ from a 5 V supply voltage at room temperature. Experimental results demonstrate that the PSRR of the voltage reference achieved -118 dB at frequencies up to 1 kHz and -55 dB at 1 MHz without additional circuits for the curvature compensation. A temperature coefficient of $60 ppm/^{\circ}C$ is obtained in the range of -40 to $120^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.28-35
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• 2007

In this paper, an ultra low voltage SRAM design method based on dual-boosted cell bias technique is described. For each read/write cycle, the wordline and cell power node of the selected SRAM cells are boosted into two different voltage levels. This enhances SNM(Static Noise Margin) to a sufficient amount without an increase of the cell size, even at sub 1-V supply voltage. It also improves the SRAM circuit speed owing to increase of the cell read-out current. The proposed design technique has been demonstrated through 0.8-V, 32K-byte SRAM macro design in a $0.18-{\mu}m$ CMOS technology. Compared to the conventional cell bias technique, the simulation confirms an 135 % enhancement of the cell SNM and a 31 % faster speed at 0.8-V supply voltage. This prototype chip shows an access time of 23 ns and a power dissipation of $125\;{\mu}W/Hz$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.25-31
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• 2009

A low power SRAM using supply voltage charge recycling (SVCR-SRAM) scheme is proposed. It divides into two SRAM cell blocks and supplies two different powers. A supplied power is $V_{DD}$ and $V_{DD}/2$. The other is $V_{DD}/2$ and GND. When N-bit cells are accessed, the charge used in N/2-bit cells with VDD and $V_{DD}/2$ is recycled in the other N/2-bit cells with $V_{DD}/2$ and GND. The SVCR scheme is used in the power consuming parts which bit line, data bus, word line, and SRAM cells to reduce dynamic power. The other parts of SRAM use $V_{DD}$ and GND to achieve high speed. Also, the SVCR-SRAM results in reducing leakage power of SRAM cells due to the body-effect. A 64K-bit SRAM ($8K{\times}8$bits) is implemented in a $0.18{\mu}m$ CMOS process. It saves 57.4% write power and 27.6% read power at $V_{DD}=1.8V$ and f=50MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.133-137
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• 2016

Use of UV gel for nail management have been increasing gradually. In order to develop an UV lamp necessary to UV gel, in this study, we was designed circuits of the UV-LED lamp. Power supply part that supplies constant power to the several UV-LEDs, was designed the circuit with the method of DC-DC converter. Taking into account the direction of the thumb nail and the position of the little finger nail, it was placed UV-LEDs. Input power of the power supply part was used as a battery voltage of 3.8[V]. The output voltage of the power supply part was appeared in approximately 3.1[V]. And in order to examine the state of change of the output voltage according to the amount of current consumption of UV-LEDs, after inserting of load resister, the output voltage was more than about 3.0[V] in the simulation results of the power supply part while changing the resistance value.

• Journal of IKEEE
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• v.14 no.2
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• pp.51-57
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• 2010

A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.37-44
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• 2008

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.391-395
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• 2003

In this work, we have designed Gilbert cell downconversion mixer using 0.25um Anam CMOS process, we also have analyzed Conversion gain and IIP3 using Taylor series in our own unique way. Especially, bulk terminal is used as LO( Local Oscillator) input for reduction of power consumption and supply voltage. Supply voltage used in this design is lower than 1.8V and core current is less than 500uA. The simulation experiments showed that the conversion gain, IIP3, and power consumption were -1 dB, 4.46dBm, and 0.8mW, respectively.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.537-540
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• 2004

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation. we present an Interpolation type architecture. In order to overcome the problems of high speed operation further a novel encoder, a circuit for the Reference Fluctuation, an Averaging Resistor and a Track & Hold for the improved SNR are proposed. The proposed Interpolation ADC consists of Track & Holt four resistive ladders with 64 taps, 32 comparators and digital blocks. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply.