• Journal of the Korean Vacuum Society
• /
• v.1 no.2
• /
• pp.286-290
• /
• 1992

본 논문은 Al, Ag 박막에서 엘렉트로마이그레이션 현상에 의한 힐록, 기공형성과 접착력에 대하여 연구하였다. Mo 보트를 이용하여 1 $\times$ 10-7Torr의 진공도에서 전자빔 증착 기로 현미경용 유리기판에 약 1$000AA$의 두께로 Al, Ag 박막을 각각 증착하였다. Al, Ag 박 막에서 엘렉트로마이그레이션에 의한 결함을 연구하기 위하여 1 $\times$ 105(A/cm2)의 d.c. 전류 를 인가하였고 Scratch Method와 Tape Method로 Al과 Ag 박막의 접착력을 측정하였다. 가공과 힐록, 그리고 스크레치 채널은 SEM과 광학현미경 사진을 이용하여 분석하였다. Al 박막에서는 엘렉트로마이그레이션으로 힐록과 기공이 양극부분과 음극부분에서 각각 관찰되 었다. 반면에 Ag 박막에서는 Coulombic force에 의해 기공과 힐록이 양극부분과 음극부분 에서 각각 형성되어 역엘렉트로마이그레이션 현상을 보였다. 접착력은 산소 친화력이 강한 Al 박막에서 Ag 박막보다 크게 나타났다.

• Electrical & Electronic Materials
• /
• v.10 no.5
• /
• pp.481-486
• /
• 1997

This paper describes the anisotropic etching characteristics of Si in acqueous TMAH/IPA solutions. The etch rates of (100) oriented Si crystal planes decrease with increasing TMAH concentration and IPA concentration. Etchant concentration and etch temperature have a large effect on hillock density. Hillock density strongly increase with lower TMAH concentration and higher etch temperature. The etched (100) planes are covered by pyramidal-shaped hillocks below TMAH 15 wt.%, but very smooth surface is obtained TMAH 25 wt.%. The addition of IPA to TMAH solution leads to smoother surfaces of sidewalls etched planes. Undercutting ratio of pure TMAH solution is much higher than KOH. But, addition of IPA to TMAh the underrcutting ratio reduces by a factor of 3∼4. Therefore, acqueous TMAH/IPA solution is able to use as anisotropic etchant of Si because of full compability with IC fabrication process.

• Journal of the Korean Society for Precision Engineering
• /
• v.22 no.7 s.172
• /
• pp.71-78
• /
• 2005

The purpose of this study is to suggest a hyperfine maskless writing technique by using the nanoindentation and HF wet etching technique. Indents were made on the surface of Pyrex7740 glass by the hyperfine indentation process with a Berkovich diamond indenter, and they were etched in $50\;wr\%$ HF solution. After etching process, convex structure was obtained due to the deformation-induced hillock phenomena. In this study, effects of indentation process parameters (etching time, normal load, loading .ate, hold-time at the maximum load) on the morphologies of the indented surfaces after isotopic etching were investigated from an angle of deformation energies. Finally, sample characters were written to show the possibility of the application.

• Proceedings of the Korean Society for Technology of Plasticity Conference
• /
• 2005.10a
• /
• pp.182-185
• /
• 2005

Indentation pattern and line pattern were machined on borosilicate(Pyrex 7740 glass) surface using the combination of mechanical machining by $Nanoi-indenter\circledR$ XP and HF wet etching, and a etch-mask effect of the affected layer of the nano-scratched and indented Pyrex 7740 glass surface was investigated. In this study, effects of indentation and scratch process with etching time on the morphologies of the indented and scratched surfaces after isotropic etching were investigated from an angle of deformation energies.

• Korean Journal of Materials Research
• /
• v.17 no.1
• /
• pp.25-30
• /
• 2007

The in-situ scanning electron microscopy observation of real-time hillock evolution in pure hi thin films on glass substrate during Isothermal annealing was analyzed quantitatively to understand the compressive stress relaxation mechanism by focusing on the effect of Mo interlayer between Al film and glass substrate. There is a good correlation between the hillock-induced stress relaxation by in-situ scanning electron microscopy observation ana the measured stress relaxation by wafer curvature method. It is also clearly shown that the existence of Mo interlayer plays an important role in hillock formation probably due to the large difference in interfacial diffusivity of Al films.

• Journal of the Korean Vacuum Society
• /
• v.10 no.1
• /
• pp.27-30
• /
• 2001

Electromigration Phenomena in Al-1%Si thin film interconnections under DC and PDC conditions were investigated. Thin film interconnections with $SiO_2$ and PSG/$SiO_2$ dielectric passivation layer were formed by a standard photolithography process method and test line lengths were 100, 400, 800, 1200, and 1600 $\mu\textrm{m}$. The current density of $1.19\times10^7\textrm{A/cm}^2$ was stressed in Al-1%Si thin film interconnections under DC condition. The current density of $1.19\times10^7\textrm{A/cm}^2$ was also applied under PDC condition at the frequency of 1 Hz with the duty factor of 0.5. The electromigration resistance of PSG/SiO2 dielectric passivation test line was stronger than $SiO_2$ dielectric passivation test line. The lifetime under PDC was 2-4 times longer than DC condition. As the thin film interconnection line increased, the lifetime decreased and saturated over the critical length. Failure patterns by an electromigration were dominated by void-induced electrical open and hillock-induced electrical short.

• Journal of the Microelectronics and Packaging Society
• /
• v.12 no.4 s.37
• /
• pp.281-287
• /
• 2005

in-situ electromigration test was carried out for edge drift lines of eutectic SnPb solder using Scanning Electron Microscopy (SEM). The electromigration test for the eutectic SnPb solder sample was conducted at temperature of $90^{\circ}C$ and the current density of $6{\times}10^4A/cm^2$. Edge drift at cathode and hillock growth at anode were observed in-situ in a SEM chamber during electromigration test. It was clearly revealed that eutectic SnPb solder lines has an incubation stage before void formation during electromigration test, which seemed to be related to the void nucleation stage of flip chip solder electromigration behaviors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.539-539
• /
• 2008

본 논문에서는 투명전도박막의 균일한 표면특성을 확보하기 위해 광역평탄화 공정을 적용하여 투명전도 박막의 표면 거칠기를 연구하였으며 슬러리의 종류에 따른 박막의 연마특성을 연구하였다. 본 실험에서 사용된 ITO 박막은 RF Sputtering에 의해 제작되었고 하부 기판은 석영 Glass가 사용되었다. 광역평탄화를 위한 CMP 공정은 고분자 물질계열의 패드위에 슬러리입자를 공급하고 웨이퍼 캐리어에 하중을 가하며 웨이퍼의 표면을 연마하는 방법으로 가공물을 탄성패드에 누르면서 상대 운동시켜 가공물과 친화력이 우수한 부식액으로 화학적 제거를 함과 동시에 초미립자로 기계적 제거를 하는 것이다. ITO 박막의 평탄화를 위한 공정조건은 Polisher pressure 300 g/$cm^2$, 슬러리 유속 80 ml/min, 플레이튼속도 60 rpm으로 하였다. 위의 조건에 따라 공정을 진행 후 연마특성을 측정하였으며 이때 사용된 슬러리는 산화막에 사용되는 실리카슬러리와 금속연마용 슬러리인 EPL을 사용하였다. 연마율은 실리카 슬러리가 EPL슬러리에 비해 높음을 확인 하였다. CMP 공정에 의해 평탄화를 수행 할 경우 실리카슬러리와 EPL슬러리 모두 CMP전에 비해 돌출된 힐록들이 감소되었음을 알 수 있었다. 비균일도 특성은 모든 슬러리가 양호한 특성을 나타내었다. 평탄화된 박막의 표면과 거칠기 특성은 AFM(XE-200, PSIA Company) 을 이용하여 분석을 하였다.

• Journal of the Korean Vacuum Society
• /
• v.9 no.3
• /
• pp.233-236
• /
• 2000

The structural, electrical and chemical characteristics of Al alloy thin film with low impurity concentrations AlW deposited by using dc magnetron sputtering deposition are investigated for the applications as data bus line in the TFT-LCD panel. The deposited thin films show the decrease of resistivity and the increase of grain size after the RTA at $300^{\circ}C$ for 20 min.. Moreover, the resistivity of AlW does not show appreciable grain size dependence after RTA. It is concluded that the decrease of resistivity after RTA is due to the increase of grain size. The annealed AlW is found to be hillock free. And for investigating chemical attack in TFT-LCD etching processing the electric potential of AlW alloy for Ag/AgCl were investigated by cyclic voltammetry. When W wt.% of AlW alloy was higher than about 3%, the electric potential of AlW was more positive than ITO's. Therefore AlW alloy thin film can be propose to use for data bus line.

• Journal of the Korean Vacuum Society
• /
• v.9 no.3
• /
• pp.237-241
• /
• 2000

The structural, electrical and etching characteristics of Al alloy thin film with low impurity concentrations AlNd deposited by using do magnetron sputtering deposition are investigated for the applications as gate bus line in the TFt-LCD panel. And ITO thin film was deposited on AlNd, then the contact resistance was measured by Kelvin resistor. The deposited thin films show the decrease of resistivity and the increase of grain size after the RTA at $300^{\circ}C$ for 20 min. Moreover, the resistivity of AlNd does not show appreciable grain size dependence after RTA. It is concluded that the decrease of resistivity after RTA is due to the increase of grain size. The annealed AlNd is found to be hillock free. The etching profiles of AlNd was good and the minimun contact resistance was about $110\;{\mu\Omega}cm$. Calculation results reveal that the AlNd (2wt.%) thin film can be applicable to 25" SXGA class TFT-LCD panels.