• KIISE Transactions on Computing Practices
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• v.24 no.2
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• pp.67-76
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• 2018

BLE (Bluetooth Low Energy) has been extensively used for communication between mobile applications and wearable devices in IoT (Internet of Things). In developing Android applications, wearable devices, on which the applications can run, should be available because the existing Android SDK does not support any BLE emulation facility. In this study, we have designed and implemented the first Android BLE emulator. Using this, we are able to develop and test BLE-based Android applications even when without wearable devices. We have also proposed an automatic generation method of Android BLE scenarios based on graph model. We have shown that the method is useful for systematically testing BLE application protocols by running the generated scenarios on the Android BLE emulator.

• Proceedings of the KIEE Conference
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• 1997.07b
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• pp.654-656
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• 1997

본 논문에서는 직접신경회로망제어기(DNNC)를 사용하여 결합된 PI제어기의 이득을 구하여 보일러 터빈시스템을 제어하고자 한다. 직접신경회로망제어기는 플랜트의 동특성을 학습시키는 에뮬레이터 없이 제어입력에 대한 플랜트의 동작방향에 대한 정보만을 사용하여 신경회로망을 학습시키고, 이 신경회로망을 사용하여 제어대상 플랜트인 다중입출력플랜트를 제어하기 위하여 결합된 PI 제어기의 이득을 구한다. 컴퓨터 시뮬레이션을 통하여 제안한 알고리즘의 타당성을 입증하고자 한다.

• Journal of IKEEE
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• v.17 no.3
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• pp.324-331
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• 2013

In this paper, we implemented memristor emulator circuit on Printed Circuit Board (PCB) and observed the inherent pinched hysteresis characteristic of memristors by measuring the emulator circuit on PCB. The memristor emulator circuit implemented on PCB is composed of simple discrete devices not using any complicated circuit blocks thus we can integrate the memristor emulator circuits in very small layout area on Silicon substrate. The programmable gain amplifier is designed using the proposed memristor emulator circuit and verified that the amplifier's voltage gain can be controlled by programming memristance of the emulator circuit by circuit simulation. Threshold switching is also realized in the proposed emulator circuit thus memristance can remain unchanged when the input voltage applied to the emulator circuit is lower than VREF. The memristor emulator circuit and the programmable gain amplifier using the proposed circuit can be useful in teaching the device operation, functions, characteristics, and applications of memristors to students when thet cannot access to device and fabrication technologies of real memristors.

• Journal of Digital Contents Society
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• v.18 no.3
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• pp.607-612
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• 2017

The use of RaspberryPi in building an embedded system may be difficult for users in understanding the circuit and the hardware cost. This paper proposes a solution that can test the systems virtually. The solution consists of three elements; (i) editor, (ii) interpreter and (iii) simulator and provides nine full modules and also allows the users to configure/run/test their own circuits like real environment. The task of abstraction for modules through the actual circuit test was carried out on the basis of the data sheet and the specification provided by the manufacturer. If we can improve the level of quality of our solution, it can be useful in terms of cost reduction and easy learning. To achieve this end, the electrical physics engine, the level of interpreter that can be ported to the actual board, and a generalization of the simulation logic are required.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.49-58
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• 2015

A floating type of memristor emulator which acts like the behavior of $TiO_2$ memristor has been developed. Most of existing memristor emulators are grounded type which is built disregarding the connectivity with other memristor or other devices. The developed memristor emulator is a floating type whose output does not need to be grounded. Therefore, the emulator is able to be connected with other devices and be utilized for the interoperability test with various other circuits. To prove the floating function of the proposed memristor emulator, a Wheatstone bridge is built by connecting 4 memristor emulators in series and parallel. Also this bridge circuit suggest that it is possible to weight calculation of the neural network synapse.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.91-103
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• 2002

For massive FPGA based emulator, the interconnection architecture and the transmission method of signals between FPGA's are important elements which decide speed of emulation and extendability of emulator. Existing FPGA-based emulation system is faced the problems of which the emulation speed getting slow drastically as the complexity of circuit increases. In this paper, we proposed a new innovative emulation architecture that has high resource usage rate and makes the fast emulation Possible. The emulator with very unique hierarchical ring topology Presented here has merits to overcome FPGA pin limitation by connecting each FPGA into a set of pipelined rings, and it also makes emulation speed at the tens of MHz at least even at system level where the verification complexity can easily exceed the verification capability of designers.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.4 s.316
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• pp.10-20
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• 2007

In this paper, we propose the reference implementation of WIPI runtime engine supporting various platforms such as REX OS, Qplus and Windows. We describe the architecture of WIPI runtime engine according to each platform, and introduce the method for avoiding repetitive develoment. And we explain the implementation of a linker and a loader on REX OS and describe the runtime engine structure on Qplus, a kind of embedded linux. And we introduce the implementation of the Jlet/MIDlet emulator based on a Java virtual machine and the Clet emulator based on Windows. Finally we verify the interoperability and the perfection of the proposed reference implementation through the result of the HCT and the PCT and the normal operation of the example programs.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.24-26
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• 2015

최근 많이 활용되고 있는 라즈베리파이에 기반한 임베디드 시스템을 구축함에 있어서 사용자는 회로에 대한 이해와 하드웨어 비용이라는 측면에서 어려움을 갖게 되는 경우가 많다. 본 논문에서는 이러한 시스템을 가상으로 테스트할 수 있는 솔루션을 제안하고자 한다. 개발된 프로그램은 사용자가 실제 회로를 구성하는 것과 같이 가상의 공간에서 모듈을 배치하고 모듈 간에 선을 연결하는 것으로 회로를 구성하고 동작을 테스트할 수 있다 프로그램은 회로편집기, 인터프리터, 시뮬레이터의 세 가지 요소로 구성되어 있으며 전체 9개의 모듈을 제공하고 있다. 각각의 모듈은 제조사에서 제공하는 데이터 시트와 제원을 바탕으로 실제 회로 테스트를 거쳐 추상화하는 작업을 수행하였다. 개발된 프로그램의 품질수준을 한층 끌어올린다면 비용절감과 학습, 교육 측면에서 유용하게 이용될 수 있으며, 전기물리엔진의 구현, 실제 보드로 포팅이 가능한 수준의 인터프리터, 시뮬레이션 로직의 일반화가 필요할 것으로 판단된다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.111-114
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• 2008

This paper proposes an effective hardware scheme for gabor filter and thinning stage processing of a fingerprint identification algorithm based on minutiae with 80% cycle occupation of 32-bit RISC microprocessor. The algorithm was developed based on minutiae with bifurcation and ending point. The analysis of an algorithm source rode was performed using ARM emulator.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.11
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• pp.12-17
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• 2009

This paper presents a tag emulator for a UHF band RFID system. The tag emulator supports the 1800-6C and EPC global class 1 generation 2 standards. The transmitted signal from a reader is generated using the PIE coding and ASK modulation methods. Signals of a tag are from the FM0 coding and ASK modulation methods. The ARM7 processor carries out the overall control of the system and signal analysis of incoming data. The verification of the tag emulator employs the application platform implemented in C++. Users can define parameter values for protocol during the application run. The tag emulator presented in this paper allows evaluating various design alternatives of the target RFID system in real applications.