• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.2
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• pp.231-239
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• 1998

In this paper, we designed a current controlling servo system for speed control of a PMSM. In existing auto-tuning methods for PI controller parameters, the output response is delayed and the overshoot is generated. By solving these existing problems in this paper, a new PI auto-tuning method is applied to the speed controller for fast-response and reduced overshoot. PMSM servo systems offer a great advantage in unmanned factories where a great number of servo motors are employed, because of its easy maintenance characteristics and controllability. The implemented servo system is composed of absolute position detecting circuits of a rotor, a new auto-tuning PI control algorithm, a speed controller by using DSP, and power driving section. The proposed servo system is verified for it's practical availability by considering experimental results.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.209-218
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• 2012

Recently, the Field Programmable Stateful Logic Array (FPSLA) was proposed as one of the most promising system integration technologies which will extend the life of the Moore's law. This work is the first proposal of the FPSLA design automation flow, and the approaches to logic synthesis, synchronization, physical mapping, and automatic placement of the FPSLA designs. The synchronization at each gate for pipelining determines the x-coordinates of cells, and reduces the placement to 1-dimensional problems. The objective function and its gradients for the non-linear optimization of the net length and placement density have been remodeled for the reduced global placement problem. Also, a recursive algorithm has been proposed to legalize the placement by relaxing the density overflow of bipartite bin groups in a top-down hierarchical fashion. The proposed model and algorithm are implemented, and validated by applying them to the ACM/SIGDA benchmark designs. The output state of a gate in an FPSLA needs to be duplicated so that each fanout gate can be connected to a dedicated copy. This property has been taken into account by merging the duplicated nets into a hyperedge, and then, splitting the hyperedge into edges as the optimization progresses. This yields additional 18.4% of the cell count reduction in the most dense logic stage. The practicality of the FPSLA can be further enhanced primarily by incorporating into the logic synthesis the constraint to avoid the concentrated fains of gates on some logic stages. In addition, an efficient algorithm needs to be devised for the routing problem which is based on a complicated graph. The graph models the nanowire crossbar which is trimmed to be embedded into the FPSLA fabric, and therefore, asymmetric. These CAD tools can be used to evaluate the fabric efficiency during the architecture enhancement as well as automate the design.

• Journal of KIISE:Software and Applications
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• v.27 no.6
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• pp.642-650
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• 2000

The pilot (human actor) involved in the control loop of the highly automated aircraft systems (machine actor) must be able to monitor these systems just as the machine actor must also be able to monitor the human actor. For its safety and better performance of the human machine system, each of the two elements must be knowledgeable about the other's intentions or goals. In fact, several recent accidents occurred due to goal conflicts between human and machines in a modern avionic system. To facilitate the coordination of these actors, a computational aid was developed. The aid, which operates in a part-task simulator environment, attempts to facilitate the management of the goals and functions being performed to accomplish them. To provide an accurate knowledge of both actors' goals and their function statuses, the aid uses agent-based objects representing the elements of the cockpit operations. This paper describes the development of the flightdeck goals and functions called Agenda Management.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.2
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• pp.140-144
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• 2009

The efficient test tool is indispensable to the test driven development. The test tool is very helpful to get the advantage of the test driven development. Many traditional automation test tool does not support standard script language and are not suitable to unit test. In traditional unit test tool, a code for the test is added at the source code. Such method makes the complexity of a source code and has a problem which must modify many part of the source code when the test case is changed. In this paper, we present a design technique of a flexible unit testing tool which makes a developer can modify easily the test case by using the standard java script in test driven development. We implement the test tool by this design technique to verify the availability of this technique.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.3
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• pp.1-7
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• 2007

RFID ( Radio Frequency IDentification ) is an automatic realization technology that recognizes things or a person with data stored tag, card, label, etc that have microchip by using radio frequency. Automation and efficient data base management(DBM) of system are possible by replaces using Bar-code that is used widely with using RFID. In this paper, we designed RFID tag data format that used to recognize information of books in Library and implemented library management system. Library management system is divided checking collection of books, self-loaning books system, self-returning books system, management books information system for a librarian. RFID leader realized information of tag and transfer it to host computer through RS-232 interface. Host computer processes and operates information with middleware. System that we made is depending on executive system for a librarian.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.113-121
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• 1989

A software interface called CGI-K including device driver routines and graphics primitives for the grphic board "K" was designed, implemented in the Design Automation Laboratory of KAIST and installed on IBM PC/AT, using assembly and C language supported by TMS 34010 grphics processor. Several algorithms generating the graphics primitives such as box, circle, pie chord are proposed. The drawing speed of CGI-K on the graphic board K was found out to be three to ten times faster than that of the EGA for several examples. A 2-D graphics editor called GRIM (graphics input and modification) and a 3-dimensional graphics renderer called IPCHE which can draw 3-D objects were developed as two major application programs running on CGI-K. The graphics primitives supported in GRIM include polygon, box, circle, and ace. The IPCHE receives a 3-D objects data file and displays the 3-D object on the screen with hidden surface removal, shading, and perspective scaling.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.90-97
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• 1999

Recently, there have been many researches to automate processing and analysing image data in medical field, due to the advance of image processing techniques, the fast communication network and high performance hardware. In this paper, we design and implement the system based on the multi-layer neural network model to be able to analyze, differentiate and count blood cells in the peripheral blood image. To do these, we segment red and white-blood cell in blood image acquired from microscope with CCD(Charge-coupled device) camera and then apply the various feature extraction algorithms to classify. In addition to, we reduce multi-variate feature number using PCA(Principle Component Analysis) to construct more efficient classifier. So, in this paper, we are sure that the proposed system can be applied to a pathological guided system.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• KIISE Transactions on Computing Practices
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• v.23 no.1
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• pp.1-12
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• 2017

Preventive maintenance is required for best performance of facilities in large scale industry. Ultimately, the efficiency of production is maximized by preventing the failure of facilities in advance. Typically, regular maintenance is conducted manually; however, it is hard to prevent repeated failures. Also, since measures to prevent failure depend on proactive problem-solving by the facility expert, they have limitations when the expert is absent or diagnosis error is made by an unskilled expert. Alarm system is used to aid manual facility diagnosis and early detection. However, it is not efficient in practice, since it is designed to simply collect information and is activated even with small problems. In this study, we designed and developed an automated preventive maintenance system based on expert's experience in detecting failure, determining the cause, and predicting future system failure. We also discussed the system structure designed to reuse the expert's knowledge and its applications.

• Journal of KIISE:Information Networking
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• v.30 no.6
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• pp.776-786
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• 2003

Security Evaluation System is a system that evaluates the security of the entire enterprise network domain which consists of various components and that supports a security manager or a Security Management System in making decisions about security management of the enterprise network based on the evaluation. It helps the security manager or the security management system to make a decision about how to change the configuration of the network to prevent the attack due to the security vulnerabilities of the network. Security Evaluation System checks the “current status” of the network, predicts the possible intrusion and supports decision-making about security management to prevent the intrusion in advance. In this paper we analyze the requirements of the Security Evaluation System that automates the security evaluation of the enterprise network which consists of various components and that supports decision-making about security management to prevent the intrusion, and we propose a design for it which satisfies the requirements.