• Journal of the Korean Data and Information Science Society
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• v.25 no.6
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• pp.1467-1474
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• 2014

In this paper, we consider the two computer intensive methods for extended Euclidean algdrithm. Two methods we propose are C-programming based approach and Microsoft excel based method, respectively. Thses methods are applied to the derivation of greatest commnon devisor, multiplicative inverse for modular operation and the solution of diophantine equation. Concrete investigation for extended Euclidean algorithm with the computer intensive process is given. For the application of extended Euclidean algorithm, we consider the RSA encrytion method which is still popular recently.

• Journal of Educational Research in Mathematics
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• v.23 no.1
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• pp.17-35
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• 2013

The purpose of this study was to analyze the extendibility of division algorithm and Euclid algorithm for integers to algorithms for rational numbers based on word problems of fraction division. This study serviced to upgrade professional development of elementary and secondary mathematics teachers. In this paper, fractions were used as expressions of rational numbers, and they also represent rational numbers. According to discrete context and continuous context, and measurement division and partition division etc, divisibility was classified into two types; one is an abstract algebraic point of view and the other is a generalizing view which preserves division algorithms for integers. In the second view, we raised some contextual problems that can be used in school mathematics and then we discussed division algorithm, the greatest common divisor and the least common multiple, and Euclid algorithm for fractions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.728-736
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• 2007

The more improved the Internet and the information technology, the stronger cryptographic system is required which can satisfy the information security on the platform of personal hand-held devices or smart card system. This paper introduces a case study of designing an elliptic curve cryptographic processor of a high performance that can be suitably used in a wireless communicating device or in an embedded system. To design an efficient cryptographic system, we first analyzed the operation hierarchy of the elliptic curve cryptographic system and then implemented the system by adopting a serial cell multiplier and modified Euclid divider. Simulation result shows that the system was correctly designed and it can compute thousands of operations per a secdond.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.109-112
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• 2003

본 논문에서는 확장 유클리드 알고리즘을 이용하여 VLSI 구현에 적합한 GF(2/sup m/)에서의 나눗셈 알고리즘을 제안하였다. 제안하는 나눗셈 알고리즘은 GF(2/sup m/)에서 2m-2번의 반복적인 비트 연산을 필요로 하며 입력 데이터에 의존적인 하드웨어 구조를 새로운 (m+1)-bit의 유한체 G와 H를 도입하여 간단하게 제어하도록 구현하였다. 본 논문에서 제안하는 알고리즘은 유한체 곱셈과 나눗셈이 요구되는 Error Correction Code와 암호 알고리즘에 효율적으로 적용이 가능하다. 현재 대표적으로 사용되는 기존 나눗셈 알고리즘과 비교해 볼 때 연산 시간은 비슷하지만 2-bit의 제어신호만을 필요로 하기 때문에 입력 데이터에 독립적인 O(1)의 complexity를 가짐으로 O(log₂(m+1))의 컨트롤을 갖는 다른 두 알고리즘에 비해 하드웨어 리소스 면에서 월등한 결과를 보인다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.5
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• pp.17-30
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• 2001

In this paper, we implemented a scalar multiplier needed at an elliptic curve cryptosystem over standard basis in $GF(2^{163})$. The scalar multiplier consists of a radix-16 finite field serial multiplier and a finite field inverter with some control logics. The main contribution is to develop a new fast finite field inverter, which made it possible to avoid time consuming iterations of finite field multiplication. We used an algorithmic transformation technique to obtain a data-independent computational structure of the Extended Euclid GCD algorithm. The finite field multiplier and inverter shown in this paper have regular structure so that they can be easily extended to larger word size. Moreover they can achieve 100% throughput using the pipelining. Our new scalar multiplier is synthesized using Hyundai Electronics 0.6$\mu\textrm{m}$ CMOS library, and maximum operating frequency is estimated about 140MHz. The resulting data processing performance is 64Kbps, that is it takes 2.53ms to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption & decryption and key exchange in real time embedded-processor environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.726-736
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• 2004

In this paper, we proposed a new scalar multiplier structure needed for an elliptic curve cryptosystem(ECC) over the standard basis in GF(2$^{163}$ ). It consists of a bit-serial multiplier and a divider with control logics, and the divider consumes most of the processing time. To speed up the division processing, we developed a new division algorithm based on the extended Euclid algorithm. Dynamic data dependency of the Euclid algorithm has been transformed to static and fixed data flow by a localization technique, to make it independent of the input and field polynomial. Compared to other existing scalar multipliers, the new scalar multiplier requires smaller gate counts with improved processor performance. It has been synthesized using Samsung 0.18 um CMOS technology, and the maximum operating frequency is estimated 250 MHz. The resulting performance is 148 kbps, that is, it takes 1.1 msec to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• Journal of KIISE:Databases
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• v.28 no.2
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• pp.217-232
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• 2001

본 논문에서는 시계열 데이터베이스에서 정규화 변환을 지원하는 서브시퀀스 매칭 알고리즘을 제안한다. 정규화 변환을 시계열 데이터 간의 절대적인 유클리드 거리에 관계 없이, 구성하는 값들의 상대적인 변화 추이가 유사한 패턴을 갖는 시계열 데이터를 검색하는 데에 유용하다. 기존의 서브시퀀스 매칭 알고리즘을 확장 없이 정규화 변환 서브시퀀스 매칭에 단순히 응용할 경우, 질의 결과로 반환되어야 할 서부시퀀스를 모두 찾아내지 못하는 착오 기각이 발생한다. 또한, 정규화 변환을 지원하는 기존의 전체 매칭 알고리즘의 경우, 모든 가능한 질의 시퀀스 길이 각각에 대하여 하나씩의 인덱스를 생성하여야 하므로, 저장 공간 및 데이터 시퀀스 삽입/삭제의 부담이 매우 심각하다. 본 논문에서는 인덱스 보간법을 이용하여 문제를 해결한다. 인덱스 보간법은 인덱스가 요구되는 모든 경우 중에서 적당한 간격의 일부에 대해서만 생성된 인덱스를 이용하며, 인덱스가 필요한 모든 경우에 대한 탐색을 수행하는 기법이다. 제안된 알고리즘은 몇 개의 질의 시퀀스 길이에 대해서만 각각 인덱스를 생성한 후, 이를 이용하여 모든 가능한 길이의 질의 시퀀스에 대해서 탐색을 수행한다. 이때, 착오 기각이 발생하지 않음을 증명한다. 제안된 알고리즘은 질의 시에 주어진 질의 시퀀스의 길이에 따라 생성되어 있는 인덱스 중에서 가장 적절한 것을 선택하여 탐색을 수행한다. 이때, 생성되어 있는 인덱스의 개수가 많을수록 탐색 성능이 향상된다. 필요에 따라 인덱스의 개수를 변화함으로써 탐색 성능과 저장 공간 간의 비율을 유연하게 조정할 수 있다. 질의 시퀀스의 길이 256 ~ 512중 다섯 개의 길이에 대해 인덱스를 생성하여 실험한 결과, 탐색 결과 선택률이 $10^{-2}$일 때 제안된 알고리즘의 탐색 성능이 순차 검색에 비하여 평균 2.40배, 선택률이 $10^{-5}$일 때 평균 14.6배 개선되었다. 제안된 알고리즘의 탐색 성능은 탐색 결과 선택률이 작아질수록 더욱 향상되므로, 실제 데이터베이스 응용에서의 효용성이 높다고 판단된다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.10
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• pp.1147-1156
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• 1992

In this paper, in order to apply the $\pi/4$ shift QPSK to TCM, we propose the $\pi/8$ shift 8PSK modulation technique and the trellis-coded $\pi/8$ shift 8PSK performing signal set expansion and partition by phase difference. In addition, the Viterbi decoder with branch metrics of the squared Euclidean distance of the first phase difference as well as the Lth phase different is introduced in order to improve the bit error rate(BER) performance in differential detection of the trellis-coded $\pi/8$ shift 8PSK. The proposed Viterbi decoder is conceptually the same as the sliding multiple detection by using the branch metric with first and Lth order phase difference. We investigate the performance of the uncoded $\pi/4$ shift QPSK and the trellis-coded $\pi/8$ shift 8PSK with or without the Lth phase difference metric in an additive white Gaussian noise (AWGN) using the Monte Carlo simulation. The study shows that the $\pi/4$ shift QPSK with the Trellis-code i.e. the trellis-coded $\pi/8$ shift 8PSK is an attractive scheme for power and bandlimited systems and especially, the Viterbi decoder with first and Lth phase difference metrics improves BER performance. Also, the nest proposed algorithm can be used in the TC $\pi/8$ shift 8PSK as well as TCMDPSK.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.6
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• pp.696-702
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• 2001

In this paper, we design IDEA cipher algorithm which is cryptographically superior to DES. To improve the encryption throughput, we propose an efficient design methodology for high-speed implementation of multiplicative inverse modulo $2^{15}$+1 which requires the most computing powers in IDEA. The efficient hardware architecture for the multiplicative inverse in derived from applying of Fermat's Theorem. The computing powers for multiplicative inverse in our proposal is a decrease 50% compared with the existing method based on Extended Euclid Algorithm. We implement IDEA by applying a single iterative round method and our proposal for multiplicative inverse. With a system clock frequency 20MGz, the designed hardware permits a data conversion rate of more than 116 Mbit/s. This result show that the designed device operates about 2 times than the result of the paper by H. Bonnenberg et al. From a speed point of view, out proposal for multiplicative inverse is proved to be efficient.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.581-583
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• 2017

Elliptic curve cyptography is relatively a current cryptography based on point arithmetic on elliptic curves and the Elliptic Curve Discrete Logarithm Problem (ECDLP). This discrete logarithm problems enables perfect forward secrecy which helps to easily generate key and almost impossible to revert the generation which is a great feature for privacy and protection. In this paper, we provide a lightweight Elliptic Curve Diffie-Hellman (ECDH) Key exchange generator that creates a 163 bit long shared key that can be used in an Elliptic Curve Integrated Encryption Scheme (ECIES) as well as for key agreement. The algorithm uses a fast multiplication algorithm that is small in size and also implements the extended euclidean algorithm. This proposed architecture was designed using verilog HDL, synthesized with the vivado ISE 2016.3 and was implemented on the virtex-7 FPGA board.