• Journal of the Korean Vacuum Society
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• v.20 no.1
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• pp.42-49
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• 2011

We deposited $SiN_x$ thin films by using PECVD technique at $200^{\circ}C$ with various flow ratios of the $SiH_4/N_2$ gases. The photoluminescence measurements revealed that the maximum emission wavelength shifted to long wavelength as the ratio increased, however, positions of the several peak wavelengths, such as 1.9, 2.2, 2.4, and 3.1 eV, were independent on the ratio. Changes of the photoluminescence spectra were measured in the $N_{2}-$, $H_{2}-$, and $O_2$-annealed films. The luminescence intensities increased after the annealing process. In particular, the maximum emission wavelength shifted to short wavelength after $H_{2}-$ or $O_2$-annealing. But there were still several peaks on the spectra of all annealed films, several peak positions remained to be unchanged after the annealing. As for the light emission mechanism, we have considered the defect states of the Si- and N- dangling bonds in the $SiN_x$ energy gap, so that the energy transitions from/to the conduction/valence bands and the defect states in the gap were attributed to the light emission in the $SiN_x$ films. The experimental results point to the possibility of a Si-based light emission materials for flexible Si-based electro-optic devices.

• Journal of the Korean Vacuum Society
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• v.18 no.4
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• pp.302-309
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• 2009

We fabricated a Si nano floating gate memory with Schottky barrier tunneling transistor structure. The device was consisted of Schottky barriers of Er-silicide at source/drain and Si nanoclusters in the gate stack formed by LPCVD-digital gas feeding method. Transistor operations due to the Schottky barrier tunneling were observed under small gate bias < 2V. The nonvolatile memory properties were investigated by measuring the threshold voltage shift along the gate bias voltage and time. We obtained the 10/50 mseconds for write/erase times and the memory window of $\sim5V$ under ${\pm}20\;V$ write/erase voltages. However, the memory window decreased to 0.4V after 104seconds, which was attributed to the Er-related defects in the tunneling oxide layer. Good write/erase endurance was maintained until $10^3$ write/erase times. However, the threshold voltages moved upward, and the memory window became small after more write/erase operations. Defects in the LPCVD control oxide were discussed for the endurance results. The experimental results point to the possibility of a Si nano floating gate memory with Schottky barrier tunneling transistor structure for Si nanoscale nonvolatile memory device.